advertisement
C8051F060/1/2/3/4/5/6/7
The Mode 0 baud rate is SYSCLK / 12. RX0 is forced to open-drain in Mode 0, and an external pull-up will typically be required.
Figure 22.2. UART0 Mode 0 Timing Diagram
D0 D1
MODE 0 TRANSMIT
D2 D3 D4 D5 D6 D7
RX (data out)
TX (clk out)
D1
MODE 0 RECEIVE
D2 D3 D4
RX (data in)
D0 D5
TX (clk out)
Figure 22.3. UART0 Mode 0 Interconnect
TX
C8051Fxxx
RX
CLK
DATA
Shift
Reg.
D6 D7
8 Extra Outputs
22.1.2. Mode 1: 8-Bit UART, Variable Baud Rate
Mode 1 provides standard asynchronous, full duplex communication using a total of 10 bits per data byte: one start bit, eight data bits (LSB first), and one stop bit. Data are transmitted from the TX0 pin and received at the RX0 pin. On receive, the eight data bits are stored in SBUF0 and the stop bit goes into
RB80 (SCON0.2).
Data transmission begins when an instruction writes a data byte to the SBUF0 register. The TI0 Transmit
Interrupt Flag (SCON0.1) is set at the end of the transmission (the beginning of the stop-bit time). Data reception can begin any time after the REN0 Receive Enable bit (SCON0.4) is set to logic 1. After the stop bit is received, the data byte will be loaded into the SBUF0 receive register if the following conditions are met: RI0 must be logic 0, and if SM20 is logic 1, the stop bit must be logic 1.
If these conditions are met, the eight bits of data is stored in SBUF0, the stop bit is stored in RB80 and the
RI0 flag is set. If these conditions are not met, SBUF0 and RB80 will not be loaded and the RI0 flag will not be set. An interrupt will occur if enabled when either TI0 or RI0 are set.
Figure 22.4. UART0 Mode 1 Timing Diagram
MARK
SPACE
BIT TIMES
START
BIT
BIT SAMPLING
D0 D1 D2 D3 D4 D5 D6 D7
STOP
BIT
Rev. 1.2
267
C8051F060/1/2/3/4/5/6/7
The baud rate generated in Mode 1 is a function of timer overflow. UART0 can use Timer 1 operating in 8-
Bit Auto-Reload Mode, or Timer 2, 3, or 4 operating in Auto-reload Mode to generate the baud rate (note that the TX and RX clocks are selected separately). On each timer overflow event (a rollover from all ones
- (0xFF for Timer 1, 0xFFFF for Timer 2, 3, or 4) - to zero) a clock is sent to the baud rate logic.
The transmit baud rate clock is selected using the S0TCLK1 and S0TCLK0 bits, and the receive baud rate clock is selected using the S0RCLK1 and S0RCLK0 bits.
When Timer 1 is selected as a baud rate source, the SMOD0 bit (SSTA0.4) selects whether or not to divide the Timer 1 overflow rate by two. On reset, the SMOD0 bit is logic 0, thus selecting the lower speed baud
rate by default. The SMOD0 bit affects the baud rate generated by Timer 1 as shown in Equation 22.1.
Equation 22.1. Mode 1 Baud Rate using Timer 1
When SMOD0 = 0:
Mode1_BaudRate = 1 32
⋅
Timer1_OverflowRate
When SMOD0 = 1:
Mode1_BaudRate = 1 16
⋅
Timer1_OverflowRate
The Timer 1 overflow rate is determined by the Timer 1 clock source (T1CLK) and reload value (TH1). The
frequency of T1CLK is selected as described in Section “24.1. Timer 0 and Timer 1” on page 287
. The
Timer 1 overflow rate is calculated as shown in Equation 22.2.
Equation 22.2. Timer 1 Overflow Rate
Timer1_OverflowRate = T1CLK
⁄ (
256 – TH1
)
When Timers 2, 3, or 4 are selected as a baud rate source, the baud rate is generated as shown in
Equation 22.3. Mode 1 Baud Rate using Timer 2, 3, or 4
Mode1_BaudRate = 1 16
⋅
Timer234_OverflowRate
The overflow rate for Timer 2, 3, or 4 is determined by the clock source for the timer (TnCLK) and the 16-
bit reload value stored in the RCAPn register (n = 2, 3, or 4), as shown in Equation 22.4.
Equation 22.4. Timer 2, 3, or 4 Overflow Rate
Timer234_OverflowRate = TnCLK
⁄ (
65536 – RCAPn
)
268 Rev. 1.2
advertisement
Related manuals
advertisement