3.2 Transceiver (AD6548, U501). LG KG291, KG290

3. TECHNICAL BRIEF

3.2 Transceiver (AD6548, U501)

The AD6548/9 provides a highly integrated direct conversion radio solution that combines, on a single chip, all radio and power management functions necessary to build the most com-pact GSM radio solution possible. The only external components required for a complete radio design are the Rx SAWs, PA, Switchplexer and a few passives enabling an extremely small cost effective GSM Radio solution. The AD6548/9 uses the industry proven direct conversion re-ceiver architecture of the OthelloTM family. For Quad band appli-cations the front end features four fully integrated programmable gain differential LNAs. The RF is then downconverted by quad-rature mixers and then fed to the baseband programmable-gain amplifiers and active filters for channel selection. The

Receiver output pins can be directly connected to the baseband analog processor. The Receive path features automatic calibration and tracking to remove DC offsets. The transmitter features a translation-loop architecture for di-rectly modulating baseband signals onto the integrated TX VCO.

The translation-loop modulator and TX VCO are extremely low noise removing the need for external SAW filters prior to the PA. The AD6548/9 uses a single integrated LO VCO for both the receive and the transmit circuits. The synthesizer lock times are optimized for GPRS applications up to and including class 12.

AD6548 incorporates a complete reference crystal calibration system. This allows the external VCTCXO to be replaced with a low cost crystal. No other external components are required. The AD6548 uses the traditional

VCTCXO reference source. The AD6548/9 also contains on-chip low dropout voltage regula-tors (LDOs) to deliver regulated supply voltages to the functions on chip, with a battery input voltage of between 2.9V and 5.5V.

Comprehensive power down options are included to minimize power consumption in normal use. A standard 3 wire serial interface is used to program the IC. The interface features low-voltage digital interface buffers compatible with logic levels from 1.6V to 2.9V.

Figure 2 AD6548 Block Diagram

Copyright © 2007 LG Electronics. Inc. All right reserved.

Only for training and service purposes

- 17 LGE Internal Use Only

3. TECHNICAL BRIEF

GOMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2

No Name

1 VCC_FE

2 I

Description

Front end supply (IP)

I baseband input/output

3 IB

4 VCC_BBI

5 SDATA

6 SCLK

7 SEN

8 N/C

9 VLDO3

I baseband input/output

Baseband I, TX path supply (IP)

Serial port data

Serial port clock

Serial port enable

Not connected

TX LDO Output (1)

10 TXOP_LO

11 TXOP_HI

Transmit O/P (850/900MHz)

Transmit O/P (1800/1900MHz)

12 VCC_TXVCO TX VCO supply (1)

13 VDD Serial interface supply

14 VBAT

15 VLDO1

16 VLDO2

Battery I/P for LDO reg’s

LDO regulator Output (2)

LO VCO Supply (3)

No Name

17 VCC_REF

18 VAFC/

N/C

19 REFIN

20 REFINB

21 REF_OP

22 QB

23 Q

24 VCC_BBQ

25 RX1900B

26 RX1900

27 RX1800B

28 RX1800

29 RX900B

30 RX900

31 RX850B

32 RX850

Table 1 AD6548/9 Pin Descriptions

Description

Reference Oscillator Supply (IP)

AD6548 Crystal Freq control (IP)

AD6549: Spare Pin

Crystal Connection

Crystal Connection

Reference Frequency Output

Q baseband input/output

Q baseband input/output

Baseband Q supply (IP)

PCS 1900 LNA input

PCS 1900 LNA input

DCS 1800 LNA input

DCS 1800 LNA input

E-GSM LNA input

E-GSM LNA input

GSM 850 LNA input

GSM 850 LNA input

LGE Internal Use Only - 18 Copyright © 2007 LG Electronics. Inc. All right reserved.

Only for training and service purposes