3.17 Circuit Description. LG KG291, KG290

3. TECHNICAL BRIEF

3.17 Circuit Description

♦ Baseband Circuit Description

1. Digital Baseband system ( AD6721 )

• Digital Baseband Processor - Atlas2H (AD6721)

♦

MCU Subsystem

- ARM7TDMI

- 65MHz @ 1.8V

- 16KBytes Cache

♦ DSP Subsystem

- 16-bit Fixed Point DSP Processor

- 91 MIPS at 1.8V

- 16Kword Data and 16Kword Program SRAM

- 4Kword Program Instruction Cache

♦ Peripheral Subsystem

- Support for Burst and Page Mode Flash

- Support for Pseudo SRAM

- Ciphering module for GPRS supporting GEA1 and

- GEA2 encryption algorithms

- Parallel and Serial Display Interface

- 8x8 Keypad Interface

- Four independent programmable backlights plus One

- Service Light

- Universal System Connector Interface

- Enhanced Generic Serial Port

- Dedicated SPI interface

LGE Internal Use Only - 40 Copyright © 2007 LG Electronics. Inc. All right reserved.

Only for training and service purposes


♦ Bus Arbitration

♦

2 Mbits(256Kbytes) SRAM

• Memory Interface

- A[0:23] - 24-bit width Address BUS ( Glue Logic used to A[23] Signal)

- D[0:15] - 16-bit width Data BUS

- _WR, _RD

- _ROMCS1, - Chip Select signals for Flash Memory

- _RAM_CS1 - Chip Select signal for PSRAM

- _UBS, _LBS

- CLK, _ADV, WAIT - for Burst Mode Flash Operation

•

SIM Interface

♦ SIMCLK

♦ SIMDATA

♦ SIM_RESET

♦ USB

♦

USBDP/USBDM

• USC

Copyright © 2007 LG Electronics. Inc. All right reserved.


- 41 LGE Internal Use Only


2. Analog Main Processor (ABB part of AD6721)




• Baseband Transmit section

This Section is designed to support GMSK and 8-PSK for both single-slot and multislot applications.

And it is generated in-phase and quadrature BB modulated GMSK & 8-PSK signals. The transmit channel consists of a digital GMSK & 8-PSK modulator, a matched pair of 10-bit DACs and a matched pair of reconstruction filter. The GMSK modulator which is used for GSM applications. And the 8-PSK modulator which is used for EDGE applications.

• Baseband Receive section

This section is designed to support GMSK and 8-PSK applications. And is consists of two identical

ADC channels that process baseband in-phase and quardrature input signals. Each channel consists of a coarse switched capacitor input filter, followed by a highorder sigma-delta modulator and a lowpass digital filter.

• Auxiliary section

The AD6852 Auxiliary Section includes a Phase Locked Loop, Automatic Frequency Control (AFC)

DAC, voltage reference buffers, an Auxiliary ADC, and light controllers.

♦

Low-Noise Voltage Reference and Voltage Reference Buffers

The AD6852 provides a low-noise voltage reference and several voltage buffers which produce isolated references. The REF voltage is directly used as a reference for analog voltage regulators.

The REF voltage is used along with internal reference buffers to provide references for all of the

AD6852 digital-to-analog and analog to-digital converters. The REFBB voltage is used as a reference for the baseband transmit and baseband receive section ADCs and DACs. The

REFOUT voltage is provided for use with external devices. For example, the REFOUT voltage may be applied to measure crystal temperature using a thermistor. The REFCHG voltage is also provided for use with external devices. For example, the REFCHG voltage may be applied to measure battery temperature using a thermistor. The AD6852 provides automatic activation of the

REFBB buffer. When the baseband transmit path or baseband receive path are active, the REFBB buffer is active.

♦ Automatic Frequency Control (AFC) DAC

The AD6852 AFC DAC is a 13-bit Sigma-Delta DAC that intrinsically does not exhibit differential nonlinearity. Input data stream is sent into converted via Control Serial Port. AFCDACM (0x16) and

AFCDACL (0x17 ) registers allow to fetch in bits 15-6 and 9-0 respectively. In typical applications, the AFC DAC must often remain active while all other converters are idle. To minimize system supply current in this condition, the AFC DAC may operate with the master clock idle. The AFC

DAC uses a low-power internal oscillator to maintain a stable output voltage based on the last digital input value.





♦ Temperature Sensing System

The AD6852 includes voltage reference buffers and Auxiliary ADC inputs for measuring the temperature of the system oscillator crystal (to compensate for temperature variations) and the battery temperature (for charging applications). Each of these external temperatures may be measured using an external thermistor in series with an external resistor. The temperature ranges are based on the requirements of 3GPP TS 51.010-1 version 5.2.1 Release 5 (2003-02), Annex 1

(normative): Reference test methods, A1.2: Normal and extreme Test Conditions (TC). The more narrow temperature span, + 15 ˚C to + 80 ˚C, provides for a difference between operating temperature and ambient temperature under normal test conditions of up to 45 ˚C. There are two temperature measurement channels available, TEMP1 and TEMP2. TEMP1 is chosen if the

BatTempCh bit in the AuxControl2 register (0x14) is set low. TEMP2 is chosen if the bit is high.

♦ Auxiliary Section Control Registers

The AD6852 Auxiliary ADC digital interface provides a method for making a single Auxiliary ADC measurement and a method for updating the battery condition. If a single Auxiliary ADC measurement is desired, the Auxiliary ADC channel can be selected and the Auxiliary ADC enabled. After the conversion is complete the interrupt is asserted. The result can be read from the

AuxADCM (0x18 ) and AuxADCL (0x19 ) registers. If the battery condition update is desired, the

BatCondition bit in the AuxControl2 register should be set. The battery condition is determined by reading the BatCondM (0x1A ) and BatCondL (0x1B ) registers four times.

♦

Light Controllers

The AD6852 Auxiliary Section provides three independent PWM light controllers. The PWM output controllers regulate the average current through active lights.

Minimum Output Frequency fMCLK / 262144 Hz

Maximum Output Frequency fMCLK / 256 Hz

The output frequencies of the LIGHTx PWM output controllers are set by the

Light12Period (0x2F ) and Light3Period (0x31 ) control registers.

With fMCLK = 13 MHz, frequencies ranging from 50.781 kHz to 49.591 Hz may be specified.

fLIGHT1 = ( fMCLK / 256 ) / ( Light12Period[9:0] + 1 ) fLIGHT2 = ( fMCLK / 256 ) / ( Light12Period[9:0] + 1 ) fLIGHT3 = ( fMCLK / 256 ) / ( Light3Period[9:0] + 1 )




• Audio section

This section supports communications and personal audio applications. The audio section provides an audio codec with two digital-to-analog converts and an analog-todigital converter, a ring tone volume controller, a microphone interface, and analog input and output channels.

♦ Audio Codec

The AD6852 audio codec supports communications applications with digital sample rates of 8 kHz or 16kHz. DAC 1 is used for receiving speech. An ADC is used for sending speech.

The AD6852 audio codec supports personal audio applications with digital sample rates of 8 kHz,

11.025kHz, 12 kHz, 16 kHz, 22.05 kHz, 24 kHz, 32 kHz, 44.1 kHz, or 48 kHz. DAC 1 and DAC 2 are used for monophonic audio. The channels are common in the digital section. DAC 1 and DAC

2 are used together for stereo audio, with DAC 1 decoding the left-channel digital input and DAC 2 decoding the rightchannel digital input. Audio codec operating modes can be controlled by writing

5 bit codes in the AudMode field of the AudControl1 register and in the AudMode field of the

AudControl4 register. AudControl1 programs the sampling rate and stereo or monophonic operating mode for PCM audio samples input via the ASPORT.

AudControl4 programs the sampling rate and stereo or monophonic operating mode for PCM audio samples input via the MSPORT. Receive audio signal from MIC. LG-G832 is used differential configuration. Send audio signal to Receiver. LG-G832 is used differential configuration.

It is interconnected with external device like main microphone, main receiver, speaker and headset through the AIN1P, AIN1N, AOUT1P, AOUT1N, , AOUT2P1/2, AOUT2N1/2, AIN2P, AIN2N,

AOUT3R, AOUT3L.

AIN1P, AIN1N : Main MIC positive/negative terminal AOUT1P, AOUT1N : Main Receiver positive/negative terminal. AOUAOUT1N goes to main receiver through the SPDT AOUT2P1/2,

AOUT2N1/2: Main Speaker positive/negative terminal. AOUT2P1/2, AOUT2N1/2 go to speaker through WM8951 and SPDT.

AIN2P, AIN2N : Headset MIC positive/negative terminal.





• Power Management Section

LGE Internal Use Only

Figure 4. AD6721 Voltage Regulator Assignments

- 46 Copyright © 2007 LG Electronics. Inc. All right reserved.



♦ Voltage Regulators

- DBB Core Voltage Supply

The VCORE regulator is designed to be used as the core power supply for the DBB. With the

Hermes DBB its use is always appropriate. If the AD6721 VAPPCFG terminal is pulled up to the main battery the pass device supply VAPP operates as a Core supply and can be used for this purpose. Using VAPP as the core supply in this manner has three advantages. This mode frees up the VCORE regulator for other applications such as use as a 1.8V memory supply. VAPP is dynamically scalable that is its voltage can be changed as DBB clock frequencies are scaled.

And use of VAPP off loads power dissipation from the ABB to the pass device. This can be important in power budgeting (see the Power Dissipation Budgeting Procedure section below).

- Serial Peripheral Supply

The nominal 2.8V VEXT regulator is meant to be a power supply used by various peripheral devices in a handset. In the example shown in Figure 4 VEXT is a digital I/O supply for the displays and the camera, a supply for the FM radio IC, and an I/O supply for the IrDA transceiver.

PSRAM, SRAM, NAND/NOR Flash Memory, SD/MMC, and DBB Memory Bus Supplies In the example shown in Figure 4 the stack memory device uses the VMEM (at 2.8V) supply, VCORE and the pass device VAPP supply. The SD or MMC card uses the VEXT supply. In the example

VAPP is programmed to be 1.8V nominal. Stack memory devices will have an SRAM, or PSRAM and one or two types of Flash memory, NAND flash and/or NOR flash. Stack memory devices will have a separate supply rail for each memory chip in the stack. The VCORE, VMEM and VAPP pass device regulator are all appropriate choices for use as memory supplies.

DBB USB Transceiver Supply

The VUSB regulator supplies power to the USB transceiver in the DBB. Its input is the USB

VBUS line.

- Camera Supplies

In the example in Figure 4 the camera module has three supply rails. VGP set to 2.8V is the camera analog supply used to power the camera’s sensor. VEXT is used as the I/O supply. And

VAPP set to 1.8V is the camera digital supply. The camera module used in the example is a type that does both image sensing and image processing. VGP and VAPP are both programmable voltage supplies.





- SIM Card Supply

The SIM card supply is the VSIM regulator. This regulator has been designed to meet the power supply standards established for SIM Cards.

- Microphone Power

The VMIC regulator is designed to act as a phantom bias supply for electret microphones used in handsets and headset accessories. TDMA noise immunity is a design feature of the VMIC regulator. VMIC features low output noise in the voice audio band and should be the only supply used for microphone bias.

- Radio Reference Oscillator Power

The VRF regulator is a low out put noise supply with a specified TDMA ripple rejection. It is designed to be the power supply for the system reference oscillator in the radio subsystem.

- DBB Real Time Clock Power

The VRTC regulator is included for the purpose of powering the DBB time of day clock (RTC). A recommended backup circuit for use with VRTC is described in the section below.

- ABB Analog Supply

The ABB analog circuit supply VABB is for use by the AD6721 ABB only. The sole connection to the VABB terminal should be the recommended bypass capacitor. The VABB regulator may not be utilized by any devices other than the ABB IC.

3. MCP Memory PF38F4050L0ZBQ0 (INTEL )




• 256 Mbits NOR Flash

♦

High performance Read-While-Write/Erase

- 85 ns initial access

- 52 MHz with zero wait state, 17 ns clock-todata output synchronous-burst mode

- 25 ns asynchronous-page mode

- 4-, 8-, 16-, and continuous-word burst mode

- Programmable WAIT configuration

- Buffered Enhanced Factory Programming (BEFP) at 5 µs/byte (Typ)

- 1.8 V low-power buffered programming at 7 µs/byte (Typ)

♦ Architecture

-Asymmetrically-blocked architecture

-Multiple 8-Mbit partitions: 64-Mbit and 128-Mbit devices

-Multiple 16-Mbit partitions: 256-Mbit devices

-Four 16-Kword parameter blocks: top or bottom configurations

-64-Kword main blocks

-Dual-operation: Read-While-Write (RWW) or Read-While-Erase (RWE)

-Status register for partition and device status

♦ Power

-VCC (core) = 1.7 V - 2.0 V

-VCCQ (I/O) = 2.2 V - 3.3 V

-Standby current: 30 µA (Typ) for 256-Mbit

-4-Word synchronous read current: 16 mA (Typ) at 52 MHz

-Automatic Power Savings mode

•

64 Mbits PSRAM

♦

Device Voltage

-Core: VCC = 1.8 V (Typ)

-I/O: VCCQ = 1.8 V or 3.0 V (Typ)

♦ PSRAM Performance

-70 ns initial access, 25 ns async page read at 3.0V I/O (16-Mbit PSRAM)

-65 ns initial access, 18 ns async page reads at 3.0V I/O





4. Multimedia Process IC - AI813G

• On-chip Advance Image Processor

- Max. Image Resolution: 1280(H) * 1024(V)

- Generic Sensor Interface supports: 1.3M/VGA/QVGA CMOS sensors Supports

- Support Linear (fine steps) Zoom

- Advanced DV functions

- Built-in MPEG4 and H263 Compression/Decompression Engine

- Built-in real-time JPEG Compression/Decompression Engine:

- Advanced Hardware Color DSP for Image Processing:

• On-chip LCD Controller supports

- Dual panels: main and sub

- Max. Display Resolution: 176*220 with 260K color

• Voice/Audio Functions

- Embedded Audio Codec support: AMR record/playback , AAC/MP3 playback

- Support digital (through serial bus) outputs for MP3 audio.




5. Microphone

The main microphone is soldered to the main PCB. The audio signal is passed to AIN1P(#P16),

AIN1N(#R16), AIN2P(#P15) and AIN2N(#R15) pins of AD6721.

The voltage supply 2V5_VMIC is output from AD6721. The voltage supply 2V5_JACK is output from

BH25FB1WHFV (Low Drop Output). The VIN1 and VIN2 signals are A/D converted by the Voiceband

ADC part of AD6721. The digitized speech is passed to the DSP section for processing(coding, interleaving etc.) The Microphone interface is shown in Figure 4.

2V5_VMIC

R221

1K

MIC_P

MIC_N

R227

2.2K

R231 100ohm

C222

39p

R232 100ohm

C228 0.1u

R234

2.2K

C219

39p

C215

10u

C223

39p

OB4-15L42-C33L

2

1

MIC200

AUXIP

AUXIN

2V8_VMEM

C224

27p

C225

27p

R228 0.1u

C220 0.1u

R225

3K

R229 1.5K

C226

10u

Figure 5. Microphone(main & aux)





6. Headset Jack Interface

This phone is 4-pole type earphone jack, which has four electrodes such as L.SPK, R.SPK, MIC+ and

GND. This type usually supports single-ended configuration in the audio input path, and differential or stereo configuration in the audio output path. So this phone uses single-ended audio input and stereo audio output. But when the audio input signal is entered an AD6721, it is likely to differential signal.

When headset jack is put in and pressed the hook-switch of headset, the HOOK_DETECT signal is goes to high, then the hook-switch is detected

7. Bluetooth & FM Radio (BCM2048)




Monolithic single-die integration of Bluetooth and FM Radio Bluetooth specification version 2.0+EDR compliant with provisions for future specification Integrated InConcert TM collaborative WLAN coexistence, including 802.15.2 three-wire coexistence supportARM7TDMIS-based microprocessor with integrated 192KB ROM and 40KB RAM Integrated FM and RDS/RBDS receiver with only one external capacitor, one external inductor and optional antenna matching unit76MHz to 108MHz FM bands supported(US, Europe, and Japan)

Excellent FM Radio performance with 1uV sensitivity for 26dB (S+N)/N RDS and RBDS demodulator and decoder with filter and buffering functions Automatic frequency detection for standard crystal and

TCXO values Low Power Consumption FM signal dependent mono/stereo blend along with soft mute control FM auto search and tuning function with RSSI and status indicator





8. TA /USB Charging (ISL6299)

The ISL6299 is a fully integrated low-cost single-cell Li-ion or Li-polymer battery charger. The charger accepts two power inputs, normally one from a USB (Universal Serial Bus) port and the other from a desktop cradle. The ISL6299 is an ideal charger for smart handheld devices that need to communicate with a personal computer via USB.

The ISL6299 features 28V and 7V maximum voltages for the cradle and the USB inputs respectively.

Due to the 28V rating for the cradle input, low-cost, large output tolerance adapters can be used safely. When both inputs are powered, the cradle input is used to charge the battery. The charge current is programmable for the cradle input with a small resistor. The end-of-charge current for the cradle input is also programmable by another external resistor. The charger incorporates

Thermaguard TM which protects the IC against over temperature. If the die temperature rises above a typical value of 100C, a thermal foldback function reduces the charge current automatically to prevent further temperature rise. The charger preconditions the battery with low current when the battery voltage is below 2.6V. The charger has two indication pins. The PPR (power present) pin outputs an open-drain logic LOW when either the cradle or the USB input power is attached. The CHG (charge) pin is also an open-drain output that indicates a logic LOW when the charge current is above a minimum current level. When the charge current is below the minimum current, the CHG pin indicates a logic HIGH signal and the status is latched. The latch will be reset at one of these events: (1) the part is disabled and re-enabled; (2) the selected input source has been removed and re-applied, (3) The USBON turns LOW, or (4) The BAT pin voltage falls below the CV mode threshold.







3.17 Circuit Description. LG KG291, KG290

♦ Baseband Circuit Description

Key Features

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Table of contents

3.17 Circuit Description. LG KG291, KG290

♦ Baseband Circuit Description

Key Features

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