ST7LITE49M On-chip peripherals
Note:
Note:
I
2
C control register (I2CCR)
Reset value: 0000 0000 (00h)
7
0 0 PE ENGC START
Read / Write
ACK STOP
0
ITE
Bits 7:6 = Reserved. Forced to 0 by hardware.
Bit 5 = PE Peripheral Enable bit
This bit is set and cleared by software.
0: Peripheral disabled
1: Master/Slave capability
When PE=0, all the bits of the CR register and the SR register except the Stop bit are reset.
All outputs are released while PE=0
When PE=1, the corresponding I/O pins are selected by hardware as alternate functions.
To enable the I
2
C interface, write the CR register TWICE with PE=1 as the first write only activates the interface (only PE is set).
Bit 4 = ENGC Enable general call bit
This bit is set and cleared by software. It is also cleared by hardware when the interface is disabled (PE=0). The 00h General Call address is acknowledged (01h ignored).
0: General Call disabled
1: General Call enabled
In accordance with the I
2
C standard, when GCAL addressing is enabled, an I
2
C slave can only receive data. It will not transmit data to the master.
Bit 3 = START Generation of a Start condition bit . This bit is set and cleared by software. It is also cleared by hardware when the interface is disabled (PE=0) or when the Start condition is sent (with interrupt generation if ITE=1).
● In master mode:
0: No start generation
●
1: Repeated start generation
In slave mode:
0: No start generation
1: Start generation when the bus is free
Bit 2 = ACK Acknowledge enable bit
This bit is set and cleared by software. It is also cleared by hardware when the interface is disabled (PE=0).
0: No acknowledge returned
1: Acknowledge returned after an address byte or a data byte is received
Doc ID 13562 Rev 3 117/188
On-chip peripherals ST7LITE49M
Bit 1 = STOP Generation of a Stop condition bit
This bit is set and cleared by software. It is also cleared by hardware in master mode.
Note: This bit is not cleared when the interface is disabled (PE=0).
● In master mode:
0: No stop generation
●
1: Stop generation after the current byte transfer or after the current Start condition is sent. The STOP bit is cleared by hardware when the Stop condition is sent.
In slave mode:
0: No stop generation
1: Release the SCL and SDA lines after the current byte transfer (BTF=1). In this mode the STOP bit has to be cleared by software.
Bit 0 = ITE Interrupt enable bit
This bit is set and cleared by software and cleared by hardware when the interface is disabled (PE=0).
0: Interrupts disabled
1: Interrupts enabled
Refer to
Figure 58
for the relationship between the events and the interrupt.
SCL is held low when the ADD10, SB, BTF or ADSL flags or an EV6 event (See
Figure 57
) is detected.
118/188 Doc ID 13562 Rev 3
ST7LITE49M On-chip peripherals
I
2
C status register 1 (I2CSR1)
Reset value: 0000 0000 (00h)
7
EVF ADD10 TRA BUSY BTF
Read Only
ADSL M/SL
0
SB
Bit 7 = EVF Event flag
This bit is set by hardware as soon as an event occurs. It is cleared by software reading
SR2 register in case of error event or as described in Figure 57
. It is also cleared by hardware when the interface is disabled (PE=0).
0: No event
1: One of the following events has occurred:
– BTF=1 (byte received or transmitted)
– ADSL=1 (Address matched in Slave mode while ACK=1)
– SB=1 (Start condition generated in Master mode)
– AF=1 (No acknowledge received after byte transmission)
– STOPF=1 (Stop condition detected in Slave mode)
– ARLO=1 (Arbitration lost in Master mode)
– BERR=1 (Bus error, misplaced Start or Stop condition detected)
– ADD10=1 (Master has sent header byte)
– Address byte successfully transmitted in Master mode.
Bit 6 = ADD10 10-bit addressing in Master mode
This bit is set by hardware when the master has sent the first byte in 10-bit address mode. It is cleared by software reading SR2 register followed by a write in the DR register of the second address byte. It is also cleared by hardware when the peripheral is disabled (PE=0).
0: No ADD10 event occurred.
1: Master has sent first address byte (header)
Bit 5 = TRA Transmitter/Receiver bit
When BTF is set, TRA=1 if a data byte has been transmitted. It is cleared automatically when BTF is cleared. It is also cleared by hardware after detection of Stop condition
(STOPF=1), loss of bus arbitration (ARLO=1) or when the interface is disabled (PE=0).
0: Data byte received (if BTF=1)
1: Data byte transmitted
Bit 4 = BUSY Bus busy bit
This bit is set by hardware on detection of a Start condition and cleared by hardware on detection of a Stop condition. It indicates a communication in progress on the bus. The
BUSY flag of the I2CSR1 register is cleared if a Bus Error occurs.
0: No communication on the bus
1: Communication ongoing on the bus
Doc ID 13562 Rev 3 119/188
On-chip peripherals ST7LITE49M
Bit 3 = BTF Byte transfer finished bit
This bit is set by hardware as soon as a byte is correctly received or transmitted with interrupt generation if ITE=1. It is cleared by software reading SR1 register followed by a read or write of DR register. It is also cleared by hardware when the interface is disabled (PE=0).
– Following a byte transmission, this bit is set after reception of the acknowledge clock pulse. In case an address byte is sent, this bit is set only after the EV6 event
(See
Figure 57 ). BTF is cleared by reading SR1 register followed by writing the
next byte in DR register.
– Following a byte reception, this bit is set after transmission of the acknowledge clock pulse if ACK=1. BTF is cleared by reading SR1 register followed by reading the byte from DR register.
The SCL line is held low while BTF=1.
0: byte transfer not done
1: byte transfer succeeded
Bit 2 = ADSL Address matched bit (slave mode).
This bit is set by hardware as soon as the received slave address matched with the
OAR register content or a general call is recognized. An interrupt is generated if ITE=1.
It is cleared by software reading SR1 register or by hardware when the interface is disabled (PE=0).
The SCL line is held low while ADSL=1.
0: Address mismatched or not received
1: Received address matched
Bit 1 = M/SL Master/Slave bit
This bit is set by hardware as soon as the interface is in Master mode (writing
START=1). It is cleared by hardware after detecting a Stop condition on the bus or a loss of arbitration (ARLO=1). It is also cleared when the interface is disabled (PE=0).
0: Slave mode
1: Master mode
Bit 0 = SB Start bit (master mode).
This bit is set by hardware as soon as the Start condition is generated (following a write
START=1). An interrupt is generated if ITE=1. It is cleared by software reading SR1 register followed by writing the address byte in DR register. It is also cleared by hardware when the interface is disabled (PE=0).
0: No Start condition
1: Start condition generated
120/188 Doc ID 13562 Rev 3
ST7LITE49M
Note:
On-chip peripherals
I
2
C status register 2 (I2CSR2)
Reset value: 0000 0000 (00h)
7
0 0 0 AF STOPF
Read Only
ARLO BERR
0
GCAL
Bits 7:5 = Reserved. Forced to 0 by hardware.
Bit 4 = AF Acknowledge failure bit
This bit is set by hardware when no acknowledge is returned. An interrupt is generated if ITE=1. It is cleared by software reading SR2 register or by hardware when the interface is disabled (PE=0).
The SCL line is not held low while AF=1 but by other flags (SB or BTF) that are set at the same time.
0: No acknowledge failure
1: Acknowledge failure
Bit 3 = STOPF Stop detection bit (slave mode)
This bit is set by hardware when a Stop condition is detected on the bus after an acknowledge (if ACK=1). An interrupt is generated if ITE=1. It is cleared by software reading SR2 register or by hardware when the interface is disabled (PE=0).
The SCL line is not held low while STOPF=1.
0: No Stop condition detected
1: Stop condition detected
Bit 2 = ARLO Arbitration lost bit
This bit is set by hardware when the interface loses the arbitration of the bus to another master. An interrupt is generated if ITE=1. It is cleared by software reading SR2 register or by hardware when the interface is disabled (PE=0).
After an ARLO event the interface switches back automatically to Slave mode
(M/SL=0).
The SCL line is not held low while ARLO=1.
0: No arbitration lost detected
1: Arbitration lost detected
In a Multimaster environment, when the interface is configured in master receive mode it does not perform arbitration during the reception of the Acknowledge Bit. Mishandling of the
ARLO bit from the I2CSR2 register may occur when a second master simultaneously requests the same data from the same slave and the I
2
C master does not acknowledge the data. The ARLO bit is then left at 0 instead of being set.
Bit 1 = BERR Bus error bit
This bit is set by hardware when the interface detects a misplaced Start or Stop condition. An interrupt is generated if ITE=1. It is cleared by software reading SR2 register or by hardware when the interface is disabled (PE=0).
The SCL line is not held low while BERR=1.
0: No misplaced Start or Stop condition
1: Misplaced Start or Stop condition
Doc ID 13562 Rev 3 121/188
On-chip peripherals
Note:
ST7LITE49M
If a bus error occurs, a Stop or a repeated Start condition should be generated by the
Master to re-synchronize communication, get the transmission acknowledged and the bus released for further communication
Bit 0 = GCAL General Call bit (slave mode).
This bit is set by hardware when a general call address is detected on the bus while
ENGC=1. It is cleared by hardware detecting a Stop condition (STOPF=1) or when the interface is disabled (PE=0).
0: No general call address detected on bus
1: general call address detected on bus
Note:
I
2
C clock control register (I2CCCR)
Reset value: 0000 0000 (00h)
7
FM/SM CC6 CC5 CC4 CC3 CC2 CC1
0
CC0
Read / Write
Bit 7 = FM/SM Fast/Standard I
2
C mode bit
This bit is set and cleared by software. It is not cleared when the interface is disabled
(PE=0).
0: Standard I
2
C mode
1: Fast I
2
C mode
Bits 6:0 = CC[6:0] 7-bit clock divider bits
These bits select the speed of the bus (F
SCL
) depending on the I cleared when the interface is disabled (PE=0).
2
C mode. They are not
Refer to the Electrical Characteristics section for the table of values.
The programmed F
SCL
assumes no load on SCL and SDA lines.
I
2
C data register (I2CDR)
Reset value: 0000 0000 (00h)
7
D7 D6 D5 D2 D1
0
D0 D4 D3
Read / Write
Bits 7:0 = D[7:0] 8-bit data register
These bits contain the byte to be received or transmitted on the bus.
– Transmitter mode: byte transmission start automatically when the software writes in the DR register.
– Receiver mode: the first data byte is received automatically in the DR register using the least significant bit of the address. Then, the following data bytes are received one by one after reading the DR register.
122/188 Doc ID 13562 Rev 3
ST7LITE49M
Note:
On-chip peripherals
I
2
C own address register (I2COAR1)
Reset value: 0000 0000 (00h)
7
ADD7 ADD6 ADD5 ADD4 ADD3
Read / Write
ADD2 ADD1
0
ADD0
● In 7-bit addressing mode
Bits 7:1 = ADD[7:1] Interface address . These bits define the I
2
C bus address of the interface. They are not cleared when the interface is disabled (PE=0).
Bit 0 = ADD0 Address direction bit.
This bit is don’t care, the interface acknowledges either 0 or 1. It is not cleared when the interface is disabled (PE=0).
Address 01h is always ignored.
● In 10-bit addressing mode
Bits 7:0 = ADD[7:0] Interface address . These are the least significant bits of the I
2
C bus address of the interface. They are not cleared when the interface is disabled
(PE=0).
I
2
C own address register (I2COAR2)
Reset value: 0100 0000 (40h)
7
FR1 FR0 0 0
Read / Write
0 ADD9 ADD8
0
0
Bits 7:6 = FR[1:0] Frequency bits
These bits are set by software only when the interface is disabled (PE=0). To configure the interface to I
2
C specified delays select the value corresponding to the microcontroller frequency f
CPU
.
Table 44.
Configuration of I
2
C delay times f
CPU
< 6 MHz
6 to 8 MHz
FR1
0
0
FR0
0
1
Bits 5:3 = Reserved
Bits 2:1 = ADD[9:8] Interface address
These are the most significant bits of the I
2
C bus address of the interface (10-bit mode only). They are not cleared when the interface is disabled (PE=0).
Bit 0 = Reserved.
Doc ID 13562 Rev 3 123/188
On-chip peripherals
Table 45.
I
2
C register mapping and reset values
Address
(Hex.)
Register label
7 6 5
0064h
0065h
0066h
0067h
0068h
0069h
006Ah
I2CCR
Reset value
I2CSR1
Reset value
I2CSR2
Reset value
I2CCCR
Reset value
I2COAR1
Reset value
I2COAR2
Reset value
I2CDR
Reset value
0
EVF
0
0
FM/SM
0
ADD7
0
FR1
0
MSB
0
0
ADD10
0
0
CC6
0
ADD6
0
FR0
1
0
PE
0
TRA
0
0
CC5
0
ADD5
0
0
0
4
ENGC
0
BUSY
0
AF
0
CC4
0
ADD4
0
0
0
3
START
0
BTF
0
STOPF
0
CC3
0
ADD3
0
0
0
2
ACK
0
ADSL
0
ARLO
0
CC2
0
ADD2
0
ADD9
0
0
1
STOP
0
M/SL
0
BERR
0
CC1
0
ADD1
0
ADD8
0
0
ST7LITE49M
0
0
LSB
0
ITE
0
SB
0
GCAL
0
CC0
0
ADD0
0
124/188 Doc ID 13562 Rev 3
