Functional description. STMicroelectronics ST7LITE49M

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ST7LITE49M On-chip peripherals

Refer to the CR, SR1 and SR2 registers in Section 11.4.7

. for the bit definitions.

By default the I

C interface operates in Slave mode (M/SL bit is cleared) except when it initiates a transmit or receive sequence.

First the interface frequency must be configured using the FRi bits in the OAR2 register.

Slave mode

Note:

As soon as a start condition is detected, the address is received from the SDA line and sent to the shift register; then it is compared with the address of the interface or the general call address (if selected by software).

●

In 10-bit addressing mode, the comparison includes the header sequence (11110xx0) and the two most significant bits of the address.

● Header matched the ACK bit is set.

(10-bit mode only): the interface generates an acknowledge pulse if

Address not matched

Address matched

: the interface ignores it and waits for another Start condition.

: the interface generates in sequence:

– Acknowledge pulse if the ACK bit is set.

– EVF and ADSL bits are set with an interrupt if the ITE bit is set.

Then the interface waits for a read of the SR1 register, holding the SCL line low (see

Figure 57

transfer sequencing EV1).

Next, in 7-bit mode read the DR register to determine from the least significant bit (data direction bit) if the slave must enter Receiver or Transmitter mode.

In 10-bit mode, after receiving the address sequence the slave is always in receive mode. It will enter transmit mode on receiving a repeated Start condition followed by the header sequence with matching address bits and the least significant bit set (11110xx1).

Slave receiver

●

Following the address reception and after SR1 register has been read, the slave receives bytes from the SDA line into the DR register via the internal shift register. After each byte the interface generates in sequence:

Acknowledge pulse if the ACK bit is set

EVF and BTF bits are set with an interrupt if the ITE bit is set.

Then the interface waits for a read of the SR1 register followed by a read of the DR register, holding the SCL line low

(see Figure 57 Transfer sequencing EV2).

Slave transmitter

Following the address reception and after SR1 register has been read, the slave sends bytes from the DR register to the SDA line via the internal shift register.

The slave waits for a read of the SR1 register followed by a write in the DR register, holding the SCL line low

(see Figure 57

Transfer sequencing EV3).

When the acknowledge pulse is received the EVF and BTF bits are set by hardware with an interrupt if the ITE bit is set.

Doc ID 13562 Rev 3 111/188

On-chip peripherals

Note:

ST7LITE49M

Closing slave communication

After the last data byte is transferred a stop condition is generated by the master. The interface detects this condition and sets:

EVF and STOPF bits with an interrupt if the ITE bit is set.

Then the interface waits for a read of the SR2 register (see

Figure 57

Transfer sequencing

EV4).

Error cases

●

BERR : Detection of a Stop or a Start condition during a byte transfer. In this case, the

EVF and the BERR bits are set with an interrupt if the ITE bit is set.

If it is a Stop then the interface discards the data, released the lines and waits for another Start condition.

If it is a Start then the interface discards the data and waits for the next slave address on the bus.

AF : Detection of a non-acknowledge bit. In this case, the EVF and AF bits are set with an interrupt if the ITE bit is set.

The AF bit is cleared by reading the I2CSR2 register. However, if read before the completion of the transmission, the AF flag will be set again, thus possibly generating a new interrupt. Software must ensure either that the SCL line is back at 0 before reading the SR2 register, or be able to correctly handle a second interrupt during the 9th pulse of a transmitted byte.

In both cases, SCL line is not held low; however, the SDA line can remain low if the last bits transmitted are all 0. It is then necessary to release both lines by software. The SCL line is not held low while AF=1 but by other flags (SB or BTF) that are set at the same time.