ST7LITE49M I/O ports
10.6 Interrupts
The external interrupt event generates an interrupt if the corresponding configuration is selected with DDR and OR registers and if the I bit in the CC register is cleared (RIM instruction).
Table 27.
Description of interrupt events
Interrupt event
External interrupt on selected external event
Event flag
-
Enable control bit
DDRx
ORx
Exit from
Wait
Yes
Exit from
Halt
Yes
See application notes AN1045 software implementation of I
2
C bus master, and AN1048 - software LCD driver
10.7 Device-specific I/O port configuration
The I/O port register configurations are summarized in
Section 10.7.1: Standard ports and
Section 10.7.2: Other ports .
Table 28.
PA5:0, PB7:0, PC7:4 and PC2:0 pins
Mode floating input pull-up interrupt input open-drain output push-pull output
Table 29.
PA7:6 pins
Mode floating input interrupt input open-drain output push-pull output
M
Table 30.
PC3 pin
Mode floating input pull-up input
Doc ID 13562 Rev 3
DDR
0
0
1
1
OR
0
1
0
1
DDR
0
0
1
1
DDR
0
0
OR
0
1
0
1
OR
0
1
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I/O ports ST7LITE49M
Table 30.
PC3 pin (continued)
Mode open-drain output push-pull output
Table 31.
Port configuration
Port
Port A
Port B
Port C
Pin name
PA5:0
PA7:6
PB7:0
PC7:4,
PC2:0
PC3
OR = 0 floating floating floating
Input
OR = 1 pull-up interrupt interrupt pull-up interrupt floating floating pull-up interrupt pull-up
Table 32.
I/O port register mapping and reset values
Address
(Hex.)
Register label
7 6 5 4
0000h
0001h
0002h
0003h
0004h
0005h
0006h
0007h
0008h
PADR
Reset value
PADDR
Reset value
PAOR
Reset value
PBDR
Reset value
PBDDR
Reset value
PBOR
Reset value
PCDR
Reset value
PCDDR
Reset value
PCOR
Reset value
MSB
0
MSB
0
MSB
0
MSB
0
MSB
0
MSB
0
MSB
0
MSB
0
MSB
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
3
0
0
0
0
0
0
0
0
1
DDR
1
1
OR
0
1
Output
OR = 0 OR = 1 open-drain push-pull true open-drain open-drain push-pull open-drain open-drain push-pull push-pull
2
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
LSB
0
LSB
0
LSB
0
LSB
0
LSB
0
LSB
0
LSB
0
LSB
0
LSB
0
74/188 Doc ID 13562 Rev 3
