Interrupts
8 Interrupts
ST7LITE49M
8.1 Introduction
The ST7 enhanced interrupt management provides the following features:
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●
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Hardware interrupts
Software interrupt (TRAP)
Nested or concurrent interrupt management with flexible interrupt priority and level management:
– Up to 4 software programmable nesting levels
– 13 interrupt vectors fixed by hardware
– 2 non maskable events: RESET, TRAP
This interrupt management is based on:
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●
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Bit 5 and bit 3 of the CPU CC register (I1:0),
Interrupt software priority registers (ISPRx),
Fixed interrupt vector addresses located at the high addresses of the memory mapping
(FFE0h to FFFFh) sorted by hardware priority order.
This enhanced interrupt controller guarantees full upward compatibility with the standard
(not nested) ST7 interrupt controller.
8.2
Note:
Masking and processing flow
The interrupt masking is managed by the I1 and I0 bits of the CC register and the ISPRx registers which give the interrupt software priority level of each interrupt vector (see
Table 14
). The processing flow is shown in
Figure 20
.
When an interrupt request has to be serviced:
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●
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Normal processing is suspended at the end of the current instruction execution.
The PC, X, A and CC registers are saved onto the stack.
●
I1 and I0 bits of CC register are set according to the corresponding values in the ISPRx registers of the serviced interrupt vector.
The PC is then loaded with the interrupt vector of the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to interrupt mapping table for vector addresses).
The interrupt service routine should end with the IRET instruction which causes the contents of the saved registers to be recovered from the stack.
As a consequence of the IRET instruction, the I1 and I0 bits will be restored from the stack and the program in the previous level will resume.
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ST7LITE49M Interrupts
Table 14.
Interrupt software priority levels
Interrupt software priority
Level 0 (main)
Level 1
Level 2
Level 3 (= interrupt disable)
Figure 20.
Interrupt processing flowchart
RESET
Level
Low
High
0
1
I1
1
PENDING
INTERRUPT
N
FETCH NEXT
INSTRUCTION
Y
Interrupt has the same or a lower software priority than current one
TLI
I1:0
N
Y
THE INTERRUPT
STAYS PENDING
I0
0
1
0
1
RESTORE PC, X, A, CC
FROM STACK
Y
“IRET”
N
EXECUTE
INSTRUCTION STACK PC, X, A, CC
LOAD I1:0 FROM INTERRUPT SW REG.
LOAD PC FROM INTERRUPT VECTOR
Doc ID 13562 Rev 3 49/188
