ST7LITE49M On-chip peripherals
Note:
Control register (WDGCR)
Reset value: 0111 1111 (7Fh)
7
WDGA T6 T5 T4
Read/Write
T3 T2 T1
0
T0
Bit 7 = WDGA Activation bit
This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the watchdog can generate a reset.
0: Watchdog disabled
1: Watchdog enabled
This bit is not used if the hardware watchdog option is enabled by option byte.
Bits 6:0 = T[6:0] 7-bit timer (MSB to LSB)
These bits contain the decremented value. A reset is produced when it rolls over from
40h to 3Fh (T6 becomes cleared).
Table 34.
Watchdog timer register mapping and reset values
Address
(Hex.)
Register label
7 6 5 4 3 2
0033h
WDGCR
Reset value
WDGA
0
T6
1
T5
1
T4
1
T3
1
T2
1
1
T1
1
0
T0
1
Doc ID 13562 Rev 3 77/188
