ST7LITE49M Data EEPROM
5.3.1
5.3.2
Note:
The data EEPROM memory read/write access modes are controlled by the E2LAT bit of the
EEPROM Control/Status register (EECSR). The flowchart in Figure 7
describes these different memory access modes.
Read operation (E2LAT=0)
The EEPROM can be read as a normal ROM location when the E2LAT bit of the EECSR register is cleared.
On this device, data EEPROM can also be used to execute machine code. Take care not to write to the data EEPROM while executing from it. This would result in an unexpected code being executed.
Write operation (E2LAT=1)
To access the write mode, the E2LAT bit has to be set by software (the E2PGM bit remains cleared). When a write access to the EEPROM area occurs, the value is latched inside the
32 data latches according to its address.
When PGM bit is set by the software, all the previous bytes written in the data latches (up to
32) are programmed in the EEPROM cells. The effective high address (row) is determined by the last EEPROM write sequence. To avoid wrong programming, the user must take care that all the bytes written between two programming sequences have the same high address: only the five Least Significant Bits of the address can change.
At the end of the programming cycle, the PGM and LAT bits are cleared simultaneously.
Care should be taken during the programming cycle. Writing to the same memory location will over-program the memory (logical AND between the two write access data result) because the data latches are only cleared at the end of the programming cycle and by the falling edge of the E2LAT bit. It is not possible to read the latched data (see
Figure 9 ).
Figure 7.
Data EEPROM programming flowchart
READ MODE
E2LAT=0
E2PGM=0
WRITE MODE
E2LAT=1
E2PGM=0
READ BYTES
IN EEPROM AREA
WRITE UP TO 32 BYTES
IN EEPROM AREA
(with the same 11 MSB of the address)
START PROGRAMMING CYCLE
E2LAT=1
E2PGM=1 (set by software)
0
E2LAT
1
CLEARED BY HARDWARE
Doc ID 13562 Rev 3 25/188
