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PMAC2 VME Hardware Reference Manual
Alternately, you can define an M-variable such as M99->X:$FFFD,0,4 and then read from or write to these bits with the M-variable.
PMAC2 VME Setup
On PMAC2 VME, jumpers E2 and E4 control the frequency of operation of the DSP according to the following table:
E2 E4 X:$FFFD; 0-3 True Multiplier DSP Frequency
OFF OFF 1 x2 40
On the PMAC2 VME, I54 is read at power-up to set the baud rate clock. Because this clock is derived from the CPU clock frequency, the proper setting of I54 is dependent on the CPU clock frequency as set by E2 and E4. Table 1-3 shows the settings of I54 for 40, 60, and 80 MHz CPU operation.
I54 Baud Rate for 40 MHz CPU Baud Rate for 60 MHz CPU Baud Rate for 80 MHz CPU
0 600
2 1200
3 1800* (-0.1%)
4 2400
5 3600* (-0.19%)
6 4800
8 9600
9 14,400*(-0.75%)
10 19,200
11 28,800*(-1.5%)
12 38,400
13 57,600*(-3.0%)
14 76,800
15 Disabled
* not an exact baud rate
Disabled
900
1200
1800
2400
3600
4800
7200
9600
14,400
19,200
28,800
38,400
57,600
76,800
115,200
1200
2400
3600* (-0.19%)
4800
7200* (-0.38%)
9600
14,400*(-0.75%)
19,200
28,800*(-1.5%)
38,400
57,600*(-3.0%)
76,800
115,200*(-6.0%)
153,600
Disabled
PMAC2 CPUs
The PMAC2 VME CPU communicates with the axes through specially designed custom gate array ICs, referred to as DSPGATES. Each of these ICs can handle four analog output channels, four encoders as input, and four analog-derived inputs from accessory boards. One PMAC2 VME can utilize from one to four of these gate array ICs, so specifying the hardware configuration amounts to counting the numbers and types of inputs and outputs. Up to 16 PMAC2 VMEs may be ganged together with complete synchronization, for a total of 128 axes. A PMAC2 VME may have one of three available CPU configurations. These configurations are described in the following paragraphs.
•
P/N 602398 — This is the original standard CPU board for the PMAC2 VME. It has a 20MHz clock and a battery backup RAM.
•
P/N 602405 — This is a flash memory CPU board with no battery backup. This board provides either a 40MHz or 60MHz clock.
•
P/N 602705 — The PV CPU piggyback board provides 80 MHz CPU operation and supplemental battery-backed RAM for the PMAC2 VME.
The PV CPU board gets its name from the PV package style of the Motorola 56002 DSP IC on the board.
The board is also called the Universal CPU because it can support all speeds and configurations of the
CPU section.
Introduction 3
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Table of contents
- 5 INTRODUCTION
- 5 Features
- 5 PMAC2 VME Configuration
- 5 PMAC2 VME ASICs
- 5 DSPGATE1 Servo ASIC
- 6 DSPGATE2 I/O ASIC
- 6 PMAC2 VME Board Configuration
- 7 PMAC2 VME Setup
- 7 PMAC2 CPUs
- 8 Configurations
- 8 Firmware
- 8 Option 16 Supplemental Memory
- 9 Related Technical Documentation
- 11 CONNECTORS
- 11 PMAC2 VME Connector Summary
- 12 J1/JANA (20-Pin Header)
- 13 J2/JTHW (26-Pin Header)
- 14 J3/JIO (40-Pin Header)
- 15 J4 (JMACRO) 26-Pin Header
- 15 J5/JRS232 (10-Pin Header)
- 16 J5A/JRS422 (26-Pin Header)
- 17 J6/JDISP (14-Pin Header)
- 17 J7/JHW (20-Pin Header)
- 18 J8/JEQU (10-Pin Header)
- 18 J9/JMACH1 (100-Pin Header)
- 21 J10/JMACH2 (100-Pin Header)
- 24 P1 JMACH (96-Pin Header)
- 25 P2/JMACHA (96-Pin Header)
- 26 TB1 (2/4-Pin Terminal Block)
- 26 TB2 (3-Pin Terminal Block)
- 27 JUMPER SUMMARY
- 27 E1: Card 0 Select
- 27 E2: 40 MHz/60 MHz CPU Operation
- 27 E3: Re-Initialization on Reset Control
- 27 E4 - E6: (Reserved for future use)
- 28 E7A-H through E10A-H: P2 Connector B-Row Use Select
- 28 E11-E12: JEQU Port Sink/Source Select
- 28 E13: SCLK Direction Control
- 29 E17 - E18: Serial Connector Select
- 29 E20A-I: DPRAM Byte Order Control
- 29 E39: Reset-From-Bus Enable
- 30 Option 1V Piggyback Connector Description
- 30 J11/JMACH3 (100-Pin Header)
- 33 J12/JMACH4 (100-Pin Header)
- 36 P2A/JMACHB (96-Pin Header)
- 37 OPTION 1V PIGGYBACK JUMPER SUMMARY
- 37 E14: SCLK Direction Control
- 39 PMAC2 VME CPU
- 39 Connector Summary
- 39 J2 (JEXP)