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PMAC VME Hardware Reference Manual
TB1 (2/4-Pin Terminal Block)
Notes
Reference
2 +5V Input Positive Supply Voltage Supplies all PMAC digital circuits
3
4
+12V
-12V
Input
Input
Positive Supply Voltage
Negative Supply Voltage
+12v to +15v; not required on-board; used on j1 to supply analog inputs
-12V to –15V; required for Opt-12
ADCs; used on J1 to supply analog inputs
This terminal block can be used to provide the input for the power supply for the circuits on the PMAC2 board when it is not in a bus configuration. When the PMAC2 is in a bus configuration, these supplies come through the bus connector automatically from the bus power supply; in this case, this terminal block should not be used.
TB2 (3-Pin Terminal Block)
Pin# Symbol Function
1
2
WD_NC
COM
Output
Input
Description
Watchdog Relay Out
Watchdog Return
Notes
Normally closed
+V or 0V
3
4
WD_NO
COM
Output
Input
Watchdog Relay Out
Watchdog Return
Normally open
+V or 0V
This terminal block provides the output for PMAC2’s watchdog timer relay, both normally open and normally closed contacts. The normally closed relay contact is open while PMAC2 is operating properly (it has power and the watchdog timer is not tripped) and closed when the PMAC2 is not operating properly (either it has lost power or the watchdog timer has tripped).
22 Connectors
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Table of contents
- 5 INTRODUCTION
- 5 Features
- 5 PMAC2 VME Configuration
- 5 PMAC2 VME ASICs
- 5 DSPGATE1 Servo ASIC
- 6 DSPGATE2 I/O ASIC
- 6 PMAC2 VME Board Configuration
- 7 PMAC2 VME Setup
- 7 PMAC2 CPUs
- 8 Configurations
- 8 Firmware
- 8 Option 16 Supplemental Memory
- 9 Related Technical Documentation
- 11 CONNECTORS
- 11 PMAC2 VME Connector Summary
- 12 J1/JANA (20-Pin Header)
- 13 J2/JTHW (26-Pin Header)
- 14 J3/JIO (40-Pin Header)
- 15 J4 (JMACRO) 26-Pin Header
- 15 J5/JRS232 (10-Pin Header)
- 16 J5A/JRS422 (26-Pin Header)
- 17 J6/JDISP (14-Pin Header)
- 17 J7/JHW (20-Pin Header)
- 18 J8/JEQU (10-Pin Header)
- 18 J9/JMACH1 (100-Pin Header)
- 21 J10/JMACH2 (100-Pin Header)
- 24 P1 JMACH (96-Pin Header)
- 25 P2/JMACHA (96-Pin Header)
- 26 TB1 (2/4-Pin Terminal Block)
- 26 TB2 (3-Pin Terminal Block)
- 27 JUMPER SUMMARY
- 27 E1: Card 0 Select
- 27 E2: 40 MHz/60 MHz CPU Operation
- 27 E3: Re-Initialization on Reset Control
- 27 E4 - E6: (Reserved for future use)
- 28 E7A-H through E10A-H: P2 Connector B-Row Use Select
- 28 E11-E12: JEQU Port Sink/Source Select
- 28 E13: SCLK Direction Control
- 29 E17 - E18: Serial Connector Select
- 29 E20A-I: DPRAM Byte Order Control
- 29 E39: Reset-From-Bus Enable
- 30 Option 1V Piggyback Connector Description
- 30 J11/JMACH3 (100-Pin Header)
- 33 J12/JMACH4 (100-Pin Header)
- 36 P2A/JMACHB (96-Pin Header)
- 37 OPTION 1V PIGGYBACK JUMPER SUMMARY
- 37 E14: SCLK Direction Control
- 39 PMAC2 VME CPU
- 39 Connector Summary
- 39 J2 (JEXP)