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PMAC VME Hardware Reference Manual
E7A-H through E10A-H: P2 Connector B-Row Use Select
E Point and
Physical Layout
E7A-H
Location Description
E8A-H
E9A-H
E10A-H
B5
B5
A5
A5
Jump pins 1 to 2 to use B-row of P2 connector for
JMACH pins (not compatible with 32-bit VME).
Jump pins 2 to 3 to use B-row of P2 connector for 32bit VME bus interface
Jump pins 1 to 2 to use B-row of P2 connector for
JMACH pins (not compatible with 32-bit VME).
Jump pins 2 to 3 to use B-row of P2 connector for 32bit VME bus interface
Jump pins 1 to 2 to use B-row of P2 connector for
JMACH pins (not compatible with 32-bit VME).
Jump pins 2 to 3 to use B-row of P2 connector for 32bit VME bus interface
Jump pins 1 to 2 to use B-row of P2 connector for
JMACH pins (not compatible with 32-bit VME).
Jump pins 2 to 3 to use B-row of P2 connector for 32bit VME bus interface
Note: All jumpers in the E7 to E10 families must be in the same setting.
Default
1-2 jumpers installed
1-2 jumpers installed
1-2 jumpers installed
1-2 jumpers installed
(32-bit VME)
E11-E12: JEQU Port Sink/Source Select
E Point and
Physical Layout
E11
Location Description Default
A1 Jump pins 1 to 2 for sinking driver (ULN2803A) on
JEQU port (default configuration).
Jump pins 2 to 3 for sourcing driver (UDN2981A) on
JEQU port (alternate configuration).
E12 A1 Jump pins 1 to 2 for sinking driver (ULN2803A) on
JEQU port (default configuration).
Jump pins 2 to 3 for sourcing driver (UDN2981A) on
JEQU port (alternate configuration).
E13: SCLK Direction Control
1-2 jumpers installed
1-2 jumpers installed
E Point and
Physical
Layout
E13
Location Description Default
A1 No jumper installed Remove jumper to output SCLK generated in first
ASIC on SCLK_12 and SCLK_34, or to control direction by software.
Jump pins 1 to 2 to input SCLK signal for first ASIC on SCLK_34 and output this signal on SCLK_12.
Jump pins 2 to 3 to input SCLK signal for first ASIC on SCLK_12 and output this signal on SCLK_34.
24 Jumper Summary
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Table of contents
- 5 INTRODUCTION
- 5 Features
- 5 PMAC2 VME Configuration
- 5 PMAC2 VME ASICs
- 5 DSPGATE1 Servo ASIC
- 6 DSPGATE2 I/O ASIC
- 6 PMAC2 VME Board Configuration
- 7 PMAC2 VME Setup
- 7 PMAC2 CPUs
- 8 Configurations
- 8 Firmware
- 8 Option 16 Supplemental Memory
- 9 Related Technical Documentation
- 11 CONNECTORS
- 11 PMAC2 VME Connector Summary
- 12 J1/JANA (20-Pin Header)
- 13 J2/JTHW (26-Pin Header)
- 14 J3/JIO (40-Pin Header)
- 15 J4 (JMACRO) 26-Pin Header
- 15 J5/JRS232 (10-Pin Header)
- 16 J5A/JRS422 (26-Pin Header)
- 17 J6/JDISP (14-Pin Header)
- 17 J7/JHW (20-Pin Header)
- 18 J8/JEQU (10-Pin Header)
- 18 J9/JMACH1 (100-Pin Header)
- 21 J10/JMACH2 (100-Pin Header)
- 24 P1 JMACH (96-Pin Header)
- 25 P2/JMACHA (96-Pin Header)
- 26 TB1 (2/4-Pin Terminal Block)
- 26 TB2 (3-Pin Terminal Block)
- 27 JUMPER SUMMARY
- 27 E1: Card 0 Select
- 27 E2: 40 MHz/60 MHz CPU Operation
- 27 E3: Re-Initialization on Reset Control
- 27 E4 - E6: (Reserved for future use)
- 28 E7A-H through E10A-H: P2 Connector B-Row Use Select
- 28 E11-E12: JEQU Port Sink/Source Select
- 28 E13: SCLK Direction Control
- 29 E17 - E18: Serial Connector Select
- 29 E20A-I: DPRAM Byte Order Control
- 29 E39: Reset-From-Bus Enable
- 30 Option 1V Piggyback Connector Description
- 30 J11/JMACH3 (100-Pin Header)
- 33 J12/JMACH4 (100-Pin Header)
- 36 P2A/JMACHB (96-Pin Header)
- 37 OPTION 1V PIGGYBACK JUMPER SUMMARY
- 37 E14: SCLK Direction Control
- 39 PMAC2 VME CPU
- 39 Connector Summary
- 39 J2 (JEXP)