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PMAC VME Hardware Reference Manual
J1/JANA (20-Pin Header)
Pin #
1
2
3
4
5
6
Symbol
ANAI00
ANAI01
ANAI02
ANAI03
ANAI04
ANAI05
Function
Input
Input
Input
Input
Input
Input
Description
Analog Input 0
Analog Input 1
Analog Input 2
Analog Input 3
Analog Input 4
Analog Input 5
19
20
Front View
Notes
0-5V or +/-2.5V range
0-5V or +/-2.5V range
0-5V or +/-2.5V range
0-5V or +/-2.5V range
0-5V or +/-2.5V range
0-5V or +/-2.5V range
1
2
11
12
13
14
7
8
9
10
ANAI06
ANAI07
ANAI08
ANAI09
ANAI10
ANAI11
ANAI12
ANAI13
Input
Input
Input
Input
Input
Input
Input
Input
Analog Input 6
Analog Input 7
Analog Input 8
Analog Input 9
Analog Input 10
Analog Input 11
Analog Input 12
Analog Input 13
0-5V or +/-2.5V range
0-5V or +/-2.5V range
0-5V or +/-2.5V range (1)
0-5V or +/-2.5V range (1)
0-5V or +/-2.5V range (1)
0-5V or +/-2.5V range (1)
0-5V or +/-2.5V range (1)
0-5V or +/-2.5V range (1)
15
16
17
18
ANAI14
ANAI15
GND
+12V
Input
Input
Analog Input 14
Analog Input 15
Common PMAC Common
Output Positive Supply Voltage
0-5V or +/-2.5V range (1)
0-5V or +/-2.5V range (1)
Not isolated from digital
To power external circuitry
19
20
GND
-12V
Common PMAC Common
Output Negative Supply Voltage
Not isolated from digital
To power external circuitry
The JANA connector provides the inputs for the 8 or 16 optional analog inputs on the PMAC2.
Note: Connector J1 is present only if Option 12 is ordered. Analog inputs ANAI08 to ANAI15 are present only if
Option 12A is ordered in addition to Option 12.
8 Connectors
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Table of contents
- 5 INTRODUCTION
- 5 Features
- 5 PMAC2 VME Configuration
- 5 PMAC2 VME ASICs
- 5 DSPGATE1 Servo ASIC
- 6 DSPGATE2 I/O ASIC
- 6 PMAC2 VME Board Configuration
- 7 PMAC2 VME Setup
- 7 PMAC2 CPUs
- 8 Configurations
- 8 Firmware
- 8 Option 16 Supplemental Memory
- 9 Related Technical Documentation
- 11 CONNECTORS
- 11 PMAC2 VME Connector Summary
- 12 J1/JANA (20-Pin Header)
- 13 J2/JTHW (26-Pin Header)
- 14 J3/JIO (40-Pin Header)
- 15 J4 (JMACRO) 26-Pin Header
- 15 J5/JRS232 (10-Pin Header)
- 16 J5A/JRS422 (26-Pin Header)
- 17 J6/JDISP (14-Pin Header)
- 17 J7/JHW (20-Pin Header)
- 18 J8/JEQU (10-Pin Header)
- 18 J9/JMACH1 (100-Pin Header)
- 21 J10/JMACH2 (100-Pin Header)
- 24 P1 JMACH (96-Pin Header)
- 25 P2/JMACHA (96-Pin Header)
- 26 TB1 (2/4-Pin Terminal Block)
- 26 TB2 (3-Pin Terminal Block)
- 27 JUMPER SUMMARY
- 27 E1: Card 0 Select
- 27 E2: 40 MHz/60 MHz CPU Operation
- 27 E3: Re-Initialization on Reset Control
- 27 E4 - E6: (Reserved for future use)
- 28 E7A-H through E10A-H: P2 Connector B-Row Use Select
- 28 E11-E12: JEQU Port Sink/Source Select
- 28 E13: SCLK Direction Control
- 29 E17 - E18: Serial Connector Select
- 29 E20A-I: DPRAM Byte Order Control
- 29 E39: Reset-From-Bus Enable
- 30 Option 1V Piggyback Connector Description
- 30 J11/JMACH3 (100-Pin Header)
- 33 J12/JMACH4 (100-Pin Header)
- 36 P2A/JMACHB (96-Pin Header)
- 37 OPTION 1V PIGGYBACK JUMPER SUMMARY
- 37 E14: SCLK Direction Control
- 39 PMAC2 VME CPU
- 39 Connector Summary
- 39 J2 (JEXP)