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PMAC VME Hardware Reference Manual
Option 1V Piggyback Connector Description
The following paragraphs provide a brief description of each connector on the Option 1V Piggyback card, its use, and individual pinout information (see Figure 2-2).
P17
J11 J12
J11/JMACH3 (100-Pin Header)
99
100
Pin# Symbol Function
1
2
+5V
+5V
Description
Output / Input +5V Power
Output / Input +5V Power
13
14
15
16
17
18
9
10
11
12
5
6
7
8
CHA5+
CHA5-
CHB5+
CHB5-
CHC5+
CHC5-
CHU5
CHV5
CHW5
CHT5
USER5
PLIM5
MLIM5
HOME5
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Enc 5 Pos. A Chan.
Enc 5 Neg. A Chan.
Enc 5 Pos. B Chan.
Enc 5 Neg. B Chan.
Enc 5 Pos. C Chan.
Enc 5 Neg. C Chan.
Chan 5 U Flag
Chan 5 V Flag
Chan 5 W Flag
Chan 5 T Flag
General Purpose User Flag
Positive Overtravel Limit
Negative Overtravel Limit
Home Switch Input
Accessory Flag
20
21
WD0/ Output Watchdog Output
SCLK56+ Input / Output Encoder Sample Clock
22 SCLK56- Input / Output Encoder Sample Clock
23 ADC_CLK5+ Output A/D Converter Clock
24 ADC_CLK5- Output A/D Converter Clock
1-7
1-8
1-9
1-10
1-11
1-12
1-13
1-14
1-1
1-2
1-3
1-4
1-5
1-6
1-15
JP1
1-16
1-17
1-18
1-19
1-20
1-21
1-22
1-23
1-24
1-25
1-26
1-27
1-28
1-29
1-30
1-31
1-32
P2
1
2
Front View
Notes
For external circuit or from external supply
Also pulse input
Also direction input
Index channel
Hall effect, fault code, or sub-count
Hall effect, fault code, or sub-count
Hall effect, fault code, or sub-count
Fault code, or sub-count
Hardware capture flag, or sub-count
Hardware capture flag
Hardware capture flag
Hardware capture flag
For loss of acc supply voltage
Low is PMAC Watchdog Fault
Direction controlled by PMAC2 jumper
Programmable frequency
26 Jumper Summary
PMAC2 VME Hardware Reference Manual
J11/JMACH3 (100-Pin Header)
99
100
Pin# Symbol Function
25 ADC_STB5+ Output
26 ADC_STB5- Output
27 ADC_DAA5+ Input
28 ADC_DAA5- Input
29 ADC_DAB5+ Input
30 ADC_DAB5- Input
31
32
AENA5+
AENA5-
Output
Output
Description
A/D Converter Strobe
A/D Converter Strobe
Chan A ADC Serial Data
Chan A ADC Serial Data
Chan B ADC Serial Data
Chan B ADC Serial Data
Amplifier Enable
Amplifier Enable
1
2
Front View
Notes
Programmable sequence
MSB first
MSB first
High is enable
Low is enable
59
60
61
62
55
56
57
58
49
50
51
52
DAC_CLK5+
DAC_CLK5-
DAC5A+
DAC5A-
DAC_STB5+
DAC_STB5-
DAC5B+
DAC5B-
DIR5+
DIR5-
45 PWMCBOT5+
PULSE5+
46 PWMCBOT5-
PULSE5-
+5V
+5V
+5V
+5V
CHA6+
CHA6-
CHB6+
CHB6-
CHC6+
CHC6-
CHU6
CHV6
Output
Output
Output / Input
Output / Input
Output / Input
Output / Input
Input
Input
Input
Input
Input
Input
Input
Input
Phase A Top CMD or DAC
Clock
Phase A Top CMD or DAC
Clock
Phase A Bottom CMD or DAC
A Serial Data
Phase A Bottom CMD or DAC
A Serial Data
Phase B Top CMD or DAC
Strobe
Phase B Top CMD or DAC
Strobe
Phase B Bottom CMD or DAC
B Serial Data
Phase B Bottom CMD or DAC
B Serial Data
Phase B Top CMD or PFM
Direction
Phase B Top CMD or PFM
Direction
Phase B Bottom CMD or PFM
Pulse
Phase B Bottom CMD or PFM
Pulse
Programmable function control
Programmable function control
Programmable function control
Programmable function control
Programmable function control
Programmable function control
+5V Power
+5V Power
+5V Power
+5V Power
Enc 6 Pos. A Chan.
Enc 6 Neg. A Chan.
Enc 6 Pos. B Chan.
Enc 6 Neg. B Chan.
Enc 6 Pos. C Chan.
Enc 6 Neg. C Chan.
Chan 6 U Flag
Chan 6 V Flag
For external circuit or from external supply
For external circuit or from external supply
Also pulse input
Also direction input
Index channel
Hall effect, fault code, or sub-count
Hall effect, fault code, or sub-count
Jumper Summary 27
PMAC VME Hardware Reference Manual
J11/JMACH3 (100-Pin Header)
DAC_CLK6+
DAC_CLK6-
DAC6A+
DAC6A-
DAC_STB6+
DAC_STB6-
DAC6B+
DAC6B-
DIR6+
DIR6-
PULSE6+
PULSE6-
99
100
Pin# Symbol Function Description
63
64
65
66
67
68
CHW6
CHT6
USER6
PLIM6
MLIM6
HOME6
Input
Input
Input
Input
Input
Input
Chan 6 W Flag
Chan 6 T Flag
General Purpose User Flag
Positive Overtravel Limit
Negative Overtravel Limit
Home Switch Input
Accessory Flag
70
71
WD0/ Output Watchdog Output
SCLK56+ Input / Output Encoder Sample Clock
72 SCLK56- Input / Output Encoder Sample Clock
73 ADC_CLK6+ Output A/D Converter Clock
74 ADC_CLK6- Output
75 ADC_STB6+ Output
76 ADC_STB6- Output
77 ADC_DAA6+ Input
A/D Converter Clock
A/D Converter Strobe
A/D Converter Strobe
Chan A ADC Serial Data
78 ADC_DAA6- Input
79 ADC_DAB6+ Input
80 ADC_DAB6- Input
81 AENA6+ Output
82 AENA6- Output
Chan A ADC Serial Data
Chan B ADC Serial Data
Chan B ADC Serial Data
Amplifier Enable
Amplifier Enable
Front View
Notes
Hall effect, fault code, or sub-count
Fault code, or sub-count
Hardware capture flag, or sub-count
Hardware capture flag
Hardware capture flag
Hardware capture flag
For loss of ACC supply voltage
Low is PMAC watchdog fault
Direction controlled by PMAC2 jumper
Programmable frequency
Programmable sequence
MSB first
MSB first
High is enable
Low is enable
1
2
Phase A Top CMD or DAC
Clock
Phase A Top CMD or DAC
Clock
Phase A Bottom CMD or DAC
A Serial Data
Phase A Bottom CMD or DAC
A Serial Data
Phase B Top CMD or DAC
Strobe
Phase B Top CMD or DAC
Strobe
Phase B Bottom CMD or DAC
B Serial Data
Phase B Bottom CMD or DAC c B Serial Data
Phase B Top CMD or PFM
Direction
Phase B Top CMD or PFM
Direction
Phase B Bottom CMD or PFM
Pulse
Phase B Bottom CMD or PFM
Pulse
Programmable function control
Programmable function control
Programmable function control
Programmable function control
Programmable function control
Programmable function control
28 Jumper Summary
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Table of contents
- 5 INTRODUCTION
- 5 Features
- 5 PMAC2 VME Configuration
- 5 PMAC2 VME ASICs
- 5 DSPGATE1 Servo ASIC
- 6 DSPGATE2 I/O ASIC
- 6 PMAC2 VME Board Configuration
- 7 PMAC2 VME Setup
- 7 PMAC2 CPUs
- 8 Configurations
- 8 Firmware
- 8 Option 16 Supplemental Memory
- 9 Related Technical Documentation
- 11 CONNECTORS
- 11 PMAC2 VME Connector Summary
- 12 J1/JANA (20-Pin Header)
- 13 J2/JTHW (26-Pin Header)
- 14 J3/JIO (40-Pin Header)
- 15 J4 (JMACRO) 26-Pin Header
- 15 J5/JRS232 (10-Pin Header)
- 16 J5A/JRS422 (26-Pin Header)
- 17 J6/JDISP (14-Pin Header)
- 17 J7/JHW (20-Pin Header)
- 18 J8/JEQU (10-Pin Header)
- 18 J9/JMACH1 (100-Pin Header)
- 21 J10/JMACH2 (100-Pin Header)
- 24 P1 JMACH (96-Pin Header)
- 25 P2/JMACHA (96-Pin Header)
- 26 TB1 (2/4-Pin Terminal Block)
- 26 TB2 (3-Pin Terminal Block)
- 27 JUMPER SUMMARY
- 27 E1: Card 0 Select
- 27 E2: 40 MHz/60 MHz CPU Operation
- 27 E3: Re-Initialization on Reset Control
- 27 E4 - E6: (Reserved for future use)
- 28 E7A-H through E10A-H: P2 Connector B-Row Use Select
- 28 E11-E12: JEQU Port Sink/Source Select
- 28 E13: SCLK Direction Control
- 29 E17 - E18: Serial Connector Select
- 29 E20A-I: DPRAM Byte Order Control
- 29 E39: Reset-From-Bus Enable
- 30 Option 1V Piggyback Connector Description
- 30 J11/JMACH3 (100-Pin Header)
- 33 J12/JMACH4 (100-Pin Header)
- 36 P2A/JMACHB (96-Pin Header)
- 37 OPTION 1V PIGGYBACK JUMPER SUMMARY
- 37 E14: SCLK Direction Control
- 39 PMAC2 VME CPU
- 39 Connector Summary
- 39 J2 (JEXP)