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PMAC VME Hardware Reference Manual
J5A/JRS422 (26-Pin Header)
Front View
Pin # Symbol Function Description Notes
3 RD-
4 RD+
5
11
12
13
14
7
8
9
10
SD-
CS+
CS-
RS+
RS-
DTR
INIT/
GND
DSR
Input
Input
Output
Input
Input
Output
Output
Bidirect
Input
Common
Bidirect
Receive Data
Data
Send Data
Clear to Send
Clear to Send
Req. to Send
Req. to Send
Data Term Read
PMAC Reset
PMAC Common
Data Set Ready
Diff. I/O Low True **
Diff. I/O High True *
Diff. I/O Low True **
Diff. I/O High True *
Diff. I/O High True **
Diff. I/O Low True *
Diff. I/O High True **
Diff. I/O Low True *
Tied to DSR
Low is Reset
**
Tied to DTR
Diff. I/O Low True
Diff. I/O High True
19
20
21
22
23
24
SCK-
SCK+
SERVO-
SERVO+
PHASE-
PHASE+
Bidirect
Bidirect
Bidirect
Bidirect
Bidirect
Bidirect
Special Clock
Special Clock
Servo Clock
Servo Clock
Phase Clock
Phase Clock
Diff. I/O Low True
Diff. I/O High True
Diff. I/O Low True
Diff. I/O High True
Diff. I/O Low True ***
Diff. I/O High True ***
Diff. I/O Low True ***
Diff. I/O High True ***
26 +5V Output +5vdc Supply Power supply out
This connector can be used for serial communications on a PMAC2 VME if E17 and E18 jumpers connect pins 2 and 3. If these jumpers connect pins 1 and 2, the J5 RS-232 connector should be used instead for serial communications. In addition, this connector is used to daisy chain interconnect multiple PMACs for synchronized operation.
Note: Jumpers E17 and E18 must connect pins 2 and 3 to use this port for serial communications.
12 Connectors
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Table of contents
- 5 INTRODUCTION
- 5 Features
- 5 PMAC2 VME Configuration
- 5 PMAC2 VME ASICs
- 5 DSPGATE1 Servo ASIC
- 6 DSPGATE2 I/O ASIC
- 6 PMAC2 VME Board Configuration
- 7 PMAC2 VME Setup
- 7 PMAC2 CPUs
- 8 Configurations
- 8 Firmware
- 8 Option 16 Supplemental Memory
- 9 Related Technical Documentation
- 11 CONNECTORS
- 11 PMAC2 VME Connector Summary
- 12 J1/JANA (20-Pin Header)
- 13 J2/JTHW (26-Pin Header)
- 14 J3/JIO (40-Pin Header)
- 15 J4 (JMACRO) 26-Pin Header
- 15 J5/JRS232 (10-Pin Header)
- 16 J5A/JRS422 (26-Pin Header)
- 17 J6/JDISP (14-Pin Header)
- 17 J7/JHW (20-Pin Header)
- 18 J8/JEQU (10-Pin Header)
- 18 J9/JMACH1 (100-Pin Header)
- 21 J10/JMACH2 (100-Pin Header)
- 24 P1 JMACH (96-Pin Header)
- 25 P2/JMACHA (96-Pin Header)
- 26 TB1 (2/4-Pin Terminal Block)
- 26 TB2 (3-Pin Terminal Block)
- 27 JUMPER SUMMARY
- 27 E1: Card 0 Select
- 27 E2: 40 MHz/60 MHz CPU Operation
- 27 E3: Re-Initialization on Reset Control
- 27 E4 - E6: (Reserved for future use)
- 28 E7A-H through E10A-H: P2 Connector B-Row Use Select
- 28 E11-E12: JEQU Port Sink/Source Select
- 28 E13: SCLK Direction Control
- 29 E17 - E18: Serial Connector Select
- 29 E20A-I: DPRAM Byte Order Control
- 29 E39: Reset-From-Bus Enable
- 30 Option 1V Piggyback Connector Description
- 30 J11/JMACH3 (100-Pin Header)
- 33 J12/JMACH4 (100-Pin Header)
- 36 P2A/JMACHB (96-Pin Header)
- 37 OPTION 1V PIGGYBACK JUMPER SUMMARY
- 37 E14: SCLK Direction Control
- 39 PMAC2 VME CPU
- 39 Connector Summary
- 39 J2 (JEXP)