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PMAC2 VME Hardware Reference Manual
J2/JTHW (26-Pin Header)
Pin # Symbol
3 DAT0
Function
Input
Front View
Description
PMAC
PMAC
Data-0 Input
Notes
Data Input from Mux Port Accessories
5
7
DAT1
DAT2
Input
Input
Data-1 Input
Data-2 Input
Data Input from Mux Port Accessories
Data Input from Mux Port Accessories
9 DAT3 Input Data-3 Input
10 SEL3 Output
11 DAT4 Input Data-4 Input
12 SEL4 Output
13 DAT5 Input Data-5 Input
Data Input from Mux Port Accessories
Data Input from Mux Port Accessories
Data Input from Mux Port Accessories
14 SEL5 Output
15 DAT6 Input Data-6 Input
16 SEL6 Output
17 DAT7
18 SEL7
Input Data-7 Input
Output Output
Data Input from Mux Port Accessories
Data Input from Mux Port Accessories
Address/Data Output for Mux Port Accessories
19 N.C. N.C. No
21 BRLD/
PMAC
Output Buffer Low Is Buffer Req.
23 IPLD/ Output
PMAC
In Position Low Is In Position
PMAC
25
26
+5V
INIT/
Output
Input
+5Vdc Supply
PMAC Reset
Power Supply Out
Low Is Reset
The JTHW connector provides eight inputs and eight outputs at TTL levels; typically these are used to create multiplexed I/O with accessory boards such as Acc-18 (Thumbwheel) and Acc-34 (Discrete I/O). The port I/O may also be used directly, as non-multiplexed I/O.
Connectors 9
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Table of contents
- 5 INTRODUCTION
- 5 Features
- 5 PMAC2 VME Configuration
- 5 PMAC2 VME ASICs
- 5 DSPGATE1 Servo ASIC
- 6 DSPGATE2 I/O ASIC
- 6 PMAC2 VME Board Configuration
- 7 PMAC2 VME Setup
- 7 PMAC2 CPUs
- 8 Configurations
- 8 Firmware
- 8 Option 16 Supplemental Memory
- 9 Related Technical Documentation
- 11 CONNECTORS
- 11 PMAC2 VME Connector Summary
- 12 J1/JANA (20-Pin Header)
- 13 J2/JTHW (26-Pin Header)
- 14 J3/JIO (40-Pin Header)
- 15 J4 (JMACRO) 26-Pin Header
- 15 J5/JRS232 (10-Pin Header)
- 16 J5A/JRS422 (26-Pin Header)
- 17 J6/JDISP (14-Pin Header)
- 17 J7/JHW (20-Pin Header)
- 18 J8/JEQU (10-Pin Header)
- 18 J9/JMACH1 (100-Pin Header)
- 21 J10/JMACH2 (100-Pin Header)
- 24 P1 JMACH (96-Pin Header)
- 25 P2/JMACHA (96-Pin Header)
- 26 TB1 (2/4-Pin Terminal Block)
- 26 TB2 (3-Pin Terminal Block)
- 27 JUMPER SUMMARY
- 27 E1: Card 0 Select
- 27 E2: 40 MHz/60 MHz CPU Operation
- 27 E3: Re-Initialization on Reset Control
- 27 E4 - E6: (Reserved for future use)
- 28 E7A-H through E10A-H: P2 Connector B-Row Use Select
- 28 E11-E12: JEQU Port Sink/Source Select
- 28 E13: SCLK Direction Control
- 29 E17 - E18: Serial Connector Select
- 29 E20A-I: DPRAM Byte Order Control
- 29 E39: Reset-From-Bus Enable
- 30 Option 1V Piggyback Connector Description
- 30 J11/JMACH3 (100-Pin Header)
- 33 J12/JMACH4 (100-Pin Header)
- 36 P2A/JMACHB (96-Pin Header)
- 37 OPTION 1V PIGGYBACK JUMPER SUMMARY
- 37 E14: SCLK Direction Control
- 39 PMAC2 VME CPU
- 39 Connector Summary
- 39 J2 (JEXP)