Intel 82599 10 GbE Controller Datasheet ®

Intel

®

82599 10 GbE Controller—Pin Assignment

2.1.6 SMBus

Reserved

See the AC specifications in

Section 11.4.2.2

.

Pin Name

SMBCLK

SMBD

SMBALRT_N

Ball #

AC19

AB19

AA19

Type

o/d o/d o/d

Name and Function

SMBus Clock. One clock pulse is generated for each data bit transferred.

SMBus Data. Stable during the high period of the clock (unless it is a start or stop condition).

SMBus Alert. Acts as an interrupt pin of a slave device on the SMBus.

Note:

If the SMBus is disconnected, an external pull-up should be used for the

SMBCLK, SMBD pins.

2.1.7 I

2

C

Reserved

See the I

2

C specification and

Section 11.4.2.2

for AC specifications.

Pin Name

SCL0

SDA0

SCL1

SDA1

Ball #

AB12

AA12

AD17

AC18

Type

o/d o/d o/d o/d

Name and Function

I

2

C Clock. One clock pulse is generated for each data bit transferred.

I

2

C Data. Stable during the high period of the clock (unless it is a start or stop condition).

I

2

C Clock. One clock pulse is generated for each data bit transferred.

I

2

C Data. Stable during the high period of the clock (unless it is a start or stop condition).

Note:

If the I

2

C is disconnected, an external pull-up should be used for the clock and data pins.

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