Intel 82599 10 GbE Controller Datasheet ®

Power Management—Intel

®

82599 10 GbE Controller

5.2.4 Interconnects Power Management

This section describes the power reduction techniques used by the 82599’s main interconnects.

5.2.4.1 PCIe Link Power Management

The PCIe link state follows the power management state of the device. Since the 82599 incorporates multiple PCI functions, the device power management state is defined as the power management state of the most awake function:

• If any function is in D0 state (either D0a or D0u), the PCIe link assumes the device is in D0 state.

Else,

• If the functions are in D3 state, the PCIe link assumes the device is in D3 state.

Else,

• The device is in Dr state (PE_RST_N is asserted to all functions).

The 82599 supports all PCIe power management link states:

• L0 state is used in D0u and D0a states.

• The L0s state is used in D0a and D0u states each time link conditions apply.

• The L1 state is used in D0a and D0u states each time link conditions apply, as well as in the D3 state.

• The L2 state is used in the Dr state following a transition from a D3 state if PCI-PM

PME is enabled.

• The L3 state is used in the Dr state following power up, on transition from D0a and also if PME is not enabled in other Dr transitions.

The 82599 support for Active State Link Power Management (ASLPM) is reported via the

PCIe Active State Link PM Support register loaded from EEPROM.

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Intel

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82599 10 GbE Controller—Power Management

LA N _P W R _G O O D assertion

D r

L 2

L 3

P E R S T # deassertion

P E R S T # assertion

L0

P E R S T # assertion

W rite 00b to P ow er S tate

E nable m aster A ccess

P E R S T # assertion

D 3

L 1

W rite 11b to P ow er S tate

L0

L 0s

L1

L 0s

D 0 u

D 0 a

L1

Figure 5-2 Link Power Management State Diagram

While in L0 state, the 82599 transitions the transmit lane(s) into L0s state once the idle conditions are met for a period of time defined as follows.

L0s configuration fields are:

• L0s enable — The default value of the

Active State Link PM Control

field in the PCIe

Link Control register is set to 00b (both L0s and L1 disabled). System software can later write a different value into the Link Control register. The default value is loaded on any reset of the PCI configuration registers.

• The

L0S_ENTRY_LAT

bit in the PCIe Control Register (GCR), determines L0s entry latency. When set to 0b, L0s entry latency is the same as L0s exit latency of the device at the other end of the link. When set to 1b, L0s entry latency is (L0s exit

Latency of the device at the other end of the link /4). Default value is 0b (entry latency is the same as L0s exit latency of the device at the other end of the link).

• L0s exit latency (as published in the

L0s Exit Latency

field of the Link Capabilities register) is loaded from the EEPROM. Separate values are loaded when the 82599 shares the same reference PCIe clock with its partner across the link, and when the

82599 uses a different reference clock than its partner across the link. The 82599 reports whether it uses the slot clock configuration through the

PCIe Slot Clock

Configuration

bit loaded from the

Slot_Clock_Cfg

EEPROM bit.

• L0s acceptable latency (as published in the

Endpoint L0s Acceptable Latency

field of the Device Capabilities register) is loaded from the EEPROM.

While in L0s state, the 82599 transitions the link into L1 state once the transmit lanes or both directions of the link have been in L0s state for a period of time defined in PCI configuration space loaded from the PCIe Init Configuration 1 word in the EEPROM.

The following EEPROM fields control L1 behavior:

• Act_Stat_PM_Sup — Indicates support for ASPM L1 in the PCIe configuration space

(loaded into the

Active State Link PM Support

field)

• PCIe PLL Gate Disable — Controls PCIe PLL gating while in L1 or L2 states

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