Intel 82599 10 GbE Controller Datasheet ®

Intel

®

82599 10 GbE Controller—Firmware Module

6.4.6 NC-SI Microcode Download Module

This module is pointed to by global offset 0x09 of the manageability control table.

6.4.6.1 Patch Data Size — Offset 0x0

6.4.6.2 Rx and Tx Code Size — Offset 0x1

Bits

15:8

7:0

Name

Rx Code Length

Tx Code Length

Default

0x0 Rx Code length in Dwords.

0x0 Tx Code length in Dwords.

Description Reserved

6.4.6.3 Download Data — Offset 0x2 - Data Size

Bits

15:8

Name

Download Data

Default

0x0 Download data.

Description Reserved

6.4.7 NC-SI Configuration Module

This module is pointed to by global offset 0x0A of the manageability control table.

6.4.7.1 Section Header — Offset 0x0

Bits

15:8

7:0

Name

Block CRC8

Block Length

Default

0x0

0x0 Section length in words.

Description Reserved

272 331520-004

Firmware Module—Intel

®

82599 10 GbE Controller

6.4.7.2 Rx Mode Control1 (RR_CTRL[15:0]) — Offset

0x1

Bits

15:8

7:4

3

2

1

0

Name

Reserved

Reserved

NC-SI Speed

Receive Without

Leading Zeros

Clear Rx Error

NC-SI Loopback

Enable

Default Description

Set to 0x0.

Reserved.

When set, the NC-SI MAC speed is 100 Mb/s.

When reset, NC-SI MAC speed is 10 Mb/s.

If set, packets without leading zeros (J/K/ symbols) between TXEN assertion and TXD the first preamble byte can be received.

Should be set when the Rx path is stuck because of an overflow condition.

When set, enables NC-SI Tx-to-Rx loop. All data that is transmitted from

NC-SI is returned to it.

No data is actually transmitted from NC-SI.

Reserved

6.4.7.3 Rx Mode Control2 (RR_CTRL[31:16]) — Offset

0x2

Bits

15:0

Name

Reserved

Default

0x0

Description Reserved

6.4.7.4 Tx Mode Control1 (RT_CTRL[15:0]) — Offset

0x3

Bits

15:3

2

1

0

Name

Reserved

Transmit With

Leading Zeros

Clear Tx Error

Enable Tx Pads

Default Description

Set to 0x0.

When set, sends leading zeros (J/K/ symbols) from CRS_DV assertion to the start of preamble (PHY mode).

When de-asserted, does not send leading zeros (MAC mode).

Should be set when Tx path is stuck because of an underflow condition.

Cleared by hardware when released.

When set, the NC-SI TX pads are driving. Otherwise, they are isolated.

Reserved

331520-004 273

Intel

®

82599 10 GbE Controller—Firmware Module

6.4.7.5 Tx Mode Control2 (RT_CTRL[31:16]) — Offset

0x4

Bits

15:0

Name

Reserved

Default

0x0 Set to 0x0.

Description Reserved

6.4.7.6 MAC Tx Control Reg1 (TxCntrlReg1 (15:0]) —

Offset 0x5

2:1

0

5

4

3

Bits

15:7

6

Name

Reserved

NC-SI_enable

Two_part_deferral

Append_fcs

Pad_enable

Reserved

Tx_ch_en

Default

0x0

Description

Set to 0x0.

Enable the MAC internal NC-SI mode of operation (disables external

NC-SI gasket).

When set, performs the optional two part deferral.

When set, computes and appends the FCS on Tx frames.

Pad the TX frames, which are less than the minimum frame size.

Reserved.

Tx Channel Enable.

This bit can be used to enable the Tx path of the MAC. This bit is for debug only and the recommended way to enable the Tx path is via the RT_UCTL_CTRL.TX_enable bit.

Reserved

6.4.7.7 MAC Tx Control Reg2 (TxCntrlReg1 (31:16]) —

Offset 0x6

Bits

15:0

Name

Reserved

Default

Reserved. Should be set to 0x0.

Description Reserved

274 331520-004

Firmware Module—Intel

®

82599 10 GbE Controller

6.4.7.8 NC-SI Settings — Offset 0x7

Bits

15:9

8:7

6:1

0

Reserved

Name

RMM Out Slew Rate

RMM Out Buffer Strength

Reserved

Default

0x0

01b

011111b

0b

Description

Set to 0x0.

Configuration of the NC-SI out slew-rate control.

00b = Slowest

01b = Slow

10b = Fast

11b = Fastest

Configuration of the NC-SI out buffer strength.

000001b = 2 mA

000011b = 4 mA

000111b = 6 mA

001111b = 8 mA

011111b = 10 mA

111111b = 12 mA

Set to 0b.

Reserved

331520-004 275

NOTE: This page intentionally left blank.

Intel

®

82599 10 GbE Controller—Firmware Module

276 331520-004