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PCIe Register Map—Intel
®
82599 10 GbE Controller
9.3.6.2 Expansion ROM Base Address Register (0x30;
RW)
En
Field
Reserved
Address
This register is used to define the address and size information for boot-time access to the optional Flash memory. It is enabled by EEPROM words 0x24 and 0x14 for LAN 0 and
LAN 1, respectively. This register returns a zero value for functions without an expansion
ROM window.
Bit(s)
0
10:1
31:11
RW
RW
R
RW
Init Val
0b
Description
0b = Disables expansion ROM access.
1b = Enables expansion ROM access.
0b
0b
Always read as 0b. Writes are ignored.
Read-write bits are hard wired to 0b and dependent on the memory mapping window size.
The LAN Expansion ROM spaces can be either 64 KB or up to 8 MB in powers of 2. Mapping window size is set by EEPROM word 0x0F.
9.3.7 PCIe Capabilities
The first entry of the PCI capabilities link list is pointed to by the Cap_Ptr register.
lists the capabilities supported by the 82599.
Table 9-5 PCI Capabilities List
0x40-4F
0x50-6F
0x70-8F
Address Item
PCI Power Management
MSI
MSI-X
0x50 / 0xA0
1
Next Pointer
0x70
0xA0
0xA0-DF PCIe Capabilities 0xE0 / 0x00
0xE0-0xEF VPD Capability 0x00
1. In the dummy function, the power management capability points to the PCIe capabilities.
9.3.7.1 PCI Power Management Capability
All fields are reset at full power up. All fields except PME_En and PME_Status are reset after exiting from the D3cold state. If AUX power is not supplied, the PME_En and
PME_Status fields also reset after exiting from the D3cold state. Refer to the detailed description for registers loaded from the EEPROM at initialization.
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Intel
®
82599 10 GbE Controller—PCIe Register Map
Byte Offset
0x40
0x44
Byte 3 Byte 2
Power Management Capabilities
Data
Bridge Support
Extensions
Byte 1
Next Pointer (0x50 /
0xA0)
Byte 0
Capability ID (0x01)
Power Management Control & Status
9.3.7.1.1 Capability ID Register (0x40; RO)
This field equals 0x01 indicating the linked list item as being the PCI Power Management registers.
9.3.7.1.2 Next Pointer Register (0x41; RO)
This field provides an offset to the next capability item in the capability list. This field equals for both LAN ports to 0x50 pointing to the MSI capability. In dummy function, it equals to 0xA0 pointing to the PCIe Capabilities.
9.3.7.1.3 Power Management Capabilities — PMC Register (0x42;
RO)
This field describes the device functionality during the power management states as listed in the following table. Note that each device function has its own register.
Bits
15:11
10
9
8:6
5
4
3
2:0
RW
RO
RO
RO
RO
RO
RO
RO
RO
Default Description
01001b PME_Support.
This 5-bit field indicates the power states in which the function can assert PME#.
Condition Functionality Values:
• No AUX Pwr PME at D0 and D3hot = 01001b
• AUX Pwr PME at D0, D3hot, and D3cold = 11001b
0b
0b
D2_Support.
The 82599 does not support the D2 state.
D1_Support.
The 82599 does not support the D1 state.
000b AUX Current.
Required current defined in the Data register.
1b
0b
0b
011b
DSI.
the 82599 requires its device driver to be executed following a transition to the D0 un-initialized state.
Reserved.
PME_Clock
Disabled. Hard wire to 0b.
Version.
The 82599 complies with the PCI PM specification revision 1.2.
760 331520-004
PCIe Register Map—Intel
®
82599 10 GbE Controller
9.3.7.1.4 Power Management Control / Status Register — PMCSR
(0x44; RW)
This register (shown in the following table) is used to control and monitor power management events in the device. Note that each device function has its own PMCSR.
Bits
15
14:13
12:9
8
7:4
3
2
1:0
RW
RW1CS
RO
Default Description
0b at power up
PME_Status.
This bit is set to 1b when the function detects a wake-up event independent of the state of the
PME_En
bit. Writing a 1b clears this bit.
01b Data_Scale.
This field indicates the scaling factor that’s used when interpreting the value of the Data register.
This field equals 01b (indicating 0.1 watt/units) and the Data_Select field is set to 0, 3, 4, 7, (or
8 for function 0). Otherwise, it equals 00b.
RW
RWS
0000b Data_Select.
This 4-bit field is used to select which data is to be reported through the Data register and
Data_Scale
field. These bits are writeable only when power management is enabled via the
EEPROM.
0b at power up
PME_En.
Writing a 1b to this register enables Wakeup.
RO
RO
RO
RW
0000b
0b
0b
00b
Reserved.
No_Soft_Reset.
This bit is always set to 0b to indicate that the 82599 performs an internal reset upon transitioning from D3hot to D0 via software control of the
PowerState
bits. Configuration context is lost when performing the soft reset. Upon transition from the D3hot to the D0 state, a full re-initialization sequence is needed to return the 82599 to the D0 Initialized state.
Reserved for PCIe.
PowerState.
This field is used to set and report the power state of a function as follows:
00b = D0
01b = D1 (cycle ignored if written with this value).
10b = D2 (cycle ignored if written with this value).
11b = D3
9.3.7.1.5 PMCSR_BSE Bridge Support Extensions Register (0x46;
RO)
This register is not implemented in the 82599; values set to 0x00.
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Intel
®
82599 10 GbE Controller—PCIe Register Map
9.3.7.1.6 Data Register (0x47; RO)
This optional register is used to report power consumption and heat dissipation. The reported register is controlled by the
Data_Select
field in the PMCSR; the power scale is reported in the
Data_Scale
field in the PMCSR. The data for this field is loaded from the
EEPROM if power management is enabled in the EEPROM or with a default value of 0x00.
The values for the 82599’s functions are as follows:
Function
0
1
D0 (Consume/ Dissipate) D3 (Consume/ Dissipate)
(0x0/0x4)
EEP PCIe Control Word at offset 0x06
(0x3/0x7)
EEP PCIe Control Word at offset 0x06
EEP PCIe Control Word at offset 0x06
EEP PCIe Control Word at offset 0x06
Common
(0x8)
Multi-function option:
EEP PCIe Control Word at offset 0x06
Single-function option:
0x00
0x00
Data_Scale/
Data_Select
01b
01b
Note:
For other Data_Select values the Data register output is reserved (0b).
9.3.7.2 MSI Capability
Byte Offset
0x50
0x54
0x58
0x5C
0x60
0x64
This structure is required for PCIe devices.
Byte 3 Byte 2 Byte 1 Byte 0
Capability ID (0x05)
Message Control (0x0080) Next Pointer (0x70)
Message Address
Message Upper Address
Reserved Message Data
Mask Bits
Pending Bits
9.3.7.2.1 Capability ID Register (0x50; RO)
This field equals 0x05 indicating that the linked list item as being the MSI registers.
9.3.7.2.2 Next Pointer Register (0x51; RO)
This field provides an offset to the next capability item in the capability list. Its value of
0x70 and points to MSI-X capability.
762 331520-004
PCIe Register Map—Intel
®
82599 10 GbE Controller
9.3.7.2.3 Message Control Register (0x52; RW)
These register fields are listed in the following table. Note that there is a dedicated register (per PCI function) to separately enable its MSI.
Bits
0
3:1
6:4
7
8
15:9
RW
RW
RO
RO
RO
RO
RO
Default
0b
Description
MSI Enable.
1b = Message Signaled Interrupts. The 82599 generates an MSI for interrupt assertion instead of INTx signaling.
000b
000b
1b
1b*
0b
Multiple Messages Capable. indicates a single requested message per function.
Multiple Message Enable. returns 000b to indicate that it supports a single message per function.
64-bit Capable.
A value of 1b indicates that the 82599 is capable of generating 64-bit message addresses.
MSI per-vector masking.
0b = Indicates that the 82599 is not capable of per-vector masking.
1b = Indicates that the 82599 is capable of per-vector masking.
Note:
The value is loaded from the
MSI Mask
bit in the EEPROM.
Reserved.
Reads as 0b
9.3.7.2.4 Message Address Low Register (0x54; RW)
Written by the system to indicate the lower 32 bits of the address to use for the MSI memory write transaction. The lower two bits always return 0b regardless of the write operation.
9.3.7.2.5 Message Address High Register (0x58; RW)
Written by the system to indicate the upper 32 bits of the address to use for the MSI memory write transaction.
9.3.7.2.6 Message Data Register (0x5C; RW)
Written by the system to indicate the lower 16 bits of the data written in the MSI memory write Dword transaction. The upper 16 bits of the transaction are written as 0b.
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Intel
®
82599 10 GbE Controller—PCIe Register Map
9.3.7.2.7 Mask Bits Register (0x60; RW)
The Mask Bits and Pending Bits registers enable software to disable or defer message sending on a per-vector basis. As the 82599 supports only one message, only bit 0 of these registers are implemented.
Bits
0
31:1
RW
RW
RO
Default
0b
0x0
Description
MSI Vector 0 Mask.
If set, the 82599 is prohibited from sending MSI messages.
Reserved.
9.3.7.2.8 Pending Bits Register (0x64; RW)
Bits
0
31:1
RW
RO
RO
Default
0b
0x0
Description
If set, the 82599 has a pending MSI message.
Reserved.
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