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Reset Operation—Intel
®
82599 10 GbE Controller
4.2.2.2 VF Receive Enable — PFVFRE / VF Transmit
Enable — PFVFTE
This mechanism insures that a VF cannot transmit or receive before the Tx and Rx path has been initialized by the PF.
• The PFVFRE register contains a bit per VF. When the bit is set to 0b, Rx packet assignment for the VF’s pool is disabled. When set to 1b, Rx packet assignment for the VF’s pool is enabled.
• The PFVFTE register contains a bit per VF. When the bit is set to 0b, data fetching for the VF’s pool is disabled. When set to 1b, data fetching for the VF’s pool is enabled.
Descriptor fetching for the VF pool is maintained, up to the limit of the internal descriptor queues — regardless of PFVFTE settings.
The PFVFTE and PFVFRE registers are initialized to zero (VF Tx and Rx traffic gated) following a PF reset. The relevant bits per VF are also initialized by a VF software reset or
VFLR.
4.2.3 Reset Effects
through
Table 4-6 list how resets affect the following registers and logic:
Table 4-4 Reset Effects — Common Resets
Reset Activation
EEPROM Read
LTSSM (back to detect/polling)
LAN Power
Good
PCIe
PERST#
X X
PCIe Link Data Path
PCI Configuration Registers RO
PCI Configuration Registers RW
PCIe Local Registers
Data Path
On-die Memories
MAC, PCS, Auto-Negotiation, LinkSec,
IPsec
Wake Up (PM) Context
Wake Up/Manageability Control/Status
Regs
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
6
1
In-band
PCIe Reset
FW Reset Force TCO
X
X
X
X
X
X
X
X
6
X
X
X
Notes
9
9
8
2
7
3
4, 5
331520-004 159
Intel
®
82599 10 GbE Controller—Reset Operation
Table 4-4 Reset Effects — Common Resets (Continued)
Reset Activation
Manageability Unit
LAN Disable Strapping Pins
LAN Power
Good
X
X
PCIe
PERST#
In-band
PCIe Reset
FW Reset
X
All Other Strapping Pins X
Force TCO Notes
Table 4-5 Reset Effects — Per Function Resets
Reset Activation
EEPROM Read
LTSSM (back to detect/polling)
D3 or Dr FLR or PFLR SW Reset
Link Reset or Exit from
LAN Disable
PCIe Link Data Path
PCI Configuration Registers RO
PCI Configuration Registers RW
Data path, Memory Space
On-die Memories
MAC, PCS, Auto-Negotiation, LinkSec, IPsec
Virtual Function Resources
Wake Up (PM) Context
Wake Up/Manageability Control/Status Regs
Manageability Unit
Strapping Pins
X
X
X
X 6
X
X
X
X
X 6
X
X
X
X 6
X
X
X
Notes
10
3
4,5
9
9
2
7
Table 4-6 Reset Effects -Virtual Function Resets
Reset Activation
Interrupt Registers
Queue Disable
VF Specific PCIe Configuration Space
Data Path
Statistics Registers
VFLR
X
X
X
VF SW Reset
X
X
Notes
11
12
13
14
160 331520-004
Reset Operation—Intel
®
82599 10 GbE Controller
331520-004
Note:
VFLR
won’t clear the VFMAILBOX.VFU bit. This bit should be cleared by a direct write access or by setting PFMailbox.RVFU bit. Refer to
Notes For Table 4-4 through Table 4-6:
1.
If AUX_PWR = 0b the wake up context is reset (
PME_Status
and
PME_En
bits should be 0b at reset if the
82599 does not support PME from D3cold).
2.
The following register fields do not follow the previous general rules:
•
ESDP registers- reset on LAN Power Good only.
•
LED configuration registers.
•
The
Aux Power Detected
bit in the PCIe Device Status register is reset on LAN Power Good and PCIe Reset only.
•
FLA — reset on LAN Power Good only.
•
RAH/RAL[n, where n>0], MTA[n], VFTA[n], FHFT_*[n], TDBAH/TDBAL, and RDBAH/RDVAL registers have no default value. If the functions associated with the registers are enabled they must be programmed by software. Once programmed, their value is preserved through all resets as long as power is applied.
•
Statistic registers (physical function)
3.
The wake up context is defined in the PCI Bus Power Management Interface Specification (sticky bits). It includes:
•
PME_En
bit of the Power Management Control/Status Register (PMCSR)
•
PME_Status
bit of the Power Management Control/Status Register (PMCSR)
•
Aux_En in the PCIe registers
•
The device requester ID (since it is required for the PM_PME TLP)
The shadow copies of these bits in the Wakeup Control Register are treated identically.
4.
Refers to bits in the Wake Up Control Register that are not part of the Wake-Up Context (the PME_En and
PME_Status bits). Note that the WUFC and WUC registers are not part of the Wake Up Context and are reset as part of the data path. Include also the SW_FW_SYNC and the FWSM registers.
5.
The Wake Up Status Registers include the following:
•
Wake Up Status Register
•
Wake Up Packet Length
•
Wake Up Packet Memory
6.
The MAC cluster is reset by the appropriate event only if manageability unit is disabled and the host is in a low power state with WoL disabled.
7.
The contents of the following memories are cleared to support the requirements of PCIe FLR:
•
The Tx packet buffers
•
The Rx packet buffers
•
IPsec Tx SA tables
•
IPsec Rx SA tables
8.
The following registers are part of this group:
•
SWSM
•
GCR (only bit 9 is cleared by this reset while all other fields are cleared at LAN Power Good reset)
•
GSCL_1/GSCL_2
•
GSCN_0/1/2/3
9.
Sticky bits and hardware init bits (indicated as HwInit) in the PCI Configuration registers are cleared only by
LAN Power Good reset.
10. These registers include:
•
VFEICS
•
VFEIMS
•
VFEIAC
•
VFEIAM
•
VFEITR 0-2
•
VTIVAR0
•
VFIVAR_MISC
•
VFPBACL
•
VFMailbox
11. These registers include:
•
VFEICS
161
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