Intel 82599 10 GbE Controller Datasheet ®

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Intel 82599 10 GbE Controller Datasheet ® | Manualzz

Intel

®

82599 10 GbE Controller—Software Initialization and Diagnostics

4.6.3 Initialization Sequence

The following sequence of commands is typically issued to the device by the software device driver in order to initialize the 82599 for normal operation. The major initialization steps are:

1. Disable interrupts.

2. Issue global reset and perform general configuration (see Section 4.6.3.2

).

3. Wait for EEPROM auto read completion.

4. Wait for DMA initialization done (RDRXCTL.DMAIDONE).

5. Setup the PHY and the link (see

Section 4.6.4

).

6. Initialize all statistical counters (see

Section 4.6.5

).

7. Initialize receive (see

Section 4.6.7

).

8. Initialize transmit (see

Section 4.6.8

).

9. Enable interrupts (see Section 4.6.3.1

).

4.6.3.1 Interrupts During Initialization

Most drivers disable interrupts during initialization to prevent re-entrance. Interrupts are disabled by writing to the EIMC registers. Note that the interrupts also need to be disabled after issuing a global reset, so a typical driver initialization flow is:

1. Disable interrupts.

2. Issue a global reset.

3. Disable interrupts (again).

After initialization completes, a typical driver enables the desired interrupts by writing to the IMS register.

4.6.3.2 Global Reset and General Configuration

Note:

Global Reset = software reset + link reset.

Device initialization typically starts with a software reset that puts the device into a known state and enables the device driver to continue the initialization sequence.

Following a Global Reset the Software driver should wait at least 10msec to enable smooth initialization flow.

To enable flow control, program the FCTTV, FCRTL, FCRTH, FCRTV and FCCFG registers. If flow control is not enabled, these registers should be written with 0x0. If Tx flow control is enabled then Tx CRC by hardware should be enabled as well (HLREG0.TXCRCEN = 1b).

Refer to

Section 3.7.7.3.2

through

Section 3.7.7.3.5

for the recommended setting of the

Rx packet buffer sizes and flow control thresholds. Note that FCRTH[n].RTH fields must be set by default regardless if flow control is enabled or not. Typically, FCRTH[n] default value should be equal to RXPBSIZE[n]-0x6000. FCRTH[n].FCEN should be set to 0b if flow control is not enabled as all the other registers previously indicated.

168 331520-004

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Key Features

  • Dual Port 10 GbE
  • Single port Device
  • Serial Flash Interface
  • 4-wire SPI EEPROM Interface
  • Configurable LED Operation
  • Protected EEPROM space
  • Jumbo frames(up to 15.5 KB)
  • Flow control support
  • TCP segmentation offload (up to 256 KB)
  • IPv6 support

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Frequently Answers and Questions

What type of interface does the Intel 82599 10 GbE Controller use?
The Intel 82599 10 GbE Controller uses a PCIe Base Specification 2.0 (2.5GT/s or 5GT/s) interface. It supports a bus width of x1, x2, x4, or x8.
What is the maximum jumbo frame size supported by the Intel 82599 10 GbE Controller?
The Intel 82599 10 GbE Controller supports jumbo frames of up to 15.5 KB.
Does the Intel 82599 10 GbE Controller support IPv6?
Yes, the Intel 82599 10 GbE Controller supports IPv6 for IP/TCP and IP/UDP receive checksum offload.

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