advertisement
Device Registers — PF—Intel
®
82599 10 GbE Controller
8.2 Device Registers — PF
8.2.1
Category
MSI-X
MSI-X
MSI-X
MSI-X
MSI-X
MSI-X BAR Register Summary PF
for the MSI-X BAR offset in 32-bit and 64-bit BAR options.
BAR 3 Offset
0x0000 — (N-1)*0x10
0x0004 — (N-1)*0x10
0x0008 — (N-1)*0x10
0x000C — (N-1)*0x10
0x2000 — 0x200C
Alias Offset
N/A
N/A
N/A
N/A
N/A
Abbreviation
MSIXTADD
MSIXTUADD
MSIXTMSG
MSIXTVCTRL
MSIXPBA
Name
MSIX table entry lower address.
MSIX table entry upper address.
MSIX table entry message.
MSIX table vector control.
MSI-X Pending bit array.
RW
RW
RW
RW
RW
RO
8.2.2 Registers Summary PF — BAR 0
All of the 82599's non-PCIe configuration registers are listed in the following table. These registers are ordered by grouping and are not necessarily listed in the order that they appear in the address space.
Note:
All registers should be accessed as a 32-bit width on reads with an appropriate software mask, if needed. A software read/modify/write mechanism should be invoked for partial writes.
Table 8-2 Register Summary
Offset / Alias Offset Abbreviation
General Control Registers
0x00000 / 0x00004
0x00008
0x00018
CTRL
STATUS
CTRL_EXT
0x00020
0x00028
0x00200
0x05078
ESDP
I2CCTL
LEDCTL
EXVET
Name
Device Control Register
Device Status Register
Extended Device Control
Register
Extended SDP Control
I2C Control
LED Control
Extended VLAN Ether Type
Block
Target
Target
Target
Target
Target
Target
Target
RW
Reset
Source
Page
RW
RO
RW
RW
RW
RW
RW
PERST
331520-004 523
Intel
®
82599 10 GbE Controller—Device Registers — PF
Table 8-2 Register Summary (Continued)
Offset / Alias Offset Abbreviation
EEPROM/Flash Registers
0x10010
0x10014
0x1001C
0x10114
EEC
EERD
FLA
EEMNGDATA
0x10118
0x1011C
0x01013C
0x10200
Flow Control Registers
0x0431C / 0x03008
FLMNGCTL
FLMNGDATA
FLOP
GRC
PFCTOP
Name
EEPROM/Flash Control Register
EEPROM Read Register
Flash Access Register
Manageability EEPROM Read/
Write Data
Manageability Flash Control
Register
Manageability Flash Read Data
Flash Opcode Register
General Receive Control
0x03200+4*n, n=0...3
0x03220+4*n, n=0...7
0x03260+4*n, n=0...7
0x032A0
0x0CE00
0x03D00
PCIe Registers
0x11000
0x11010
0x11014
0x011030+4*n, n=0...3
FCTTVn
FCRTL[n]
FCRTH[n]
FCRTV
TFCS
FCCFG
GCR
GSCL_1
GSCL_2
GSCL_5_8
Priority Flow Control Type
Opcode
Flow Control Transmit Timer
Value n
Flow Control Receive Threshold
Low
Flow Control Receive Threshold
High
Flow Control Refresh Threshold
Value
Transmit Flow Control Status
Flow Control Configuration
PCIe Control Register
PCIe Statistic Control Register
#1
PCIe Statistic Control Registers
#2
PCIe Statistic Control Register
#5...#8
Block
FLEEP
FLEEP
FLEEP
FLEEP
FLEEP
FLEEP
FLEEP
FLEEP
MAC
DBU-Rx
DBU-Rx
DBU-Rx
DBU-Rx
DBU-Tx
DBU-Rx
PCIe
PCIe
PCIe
PCIe
RW
Reset
Source
Page
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RO
RW
RW
524 331520-004
Device Registers — PF—Intel
®
82599 10 GbE Controller
Table 8-2 Register Summary (Continued)
Offset / Alias Offset Abbreviation
0x11020+4*n, n=0...3
0x10150
0x11040
0x11044
0x10140
0x10148
0x10160
0x11050
0x11064
0x110B0
0x110B8
Interrupt Registers
0x00800
GSCN_0_3
FACTPS
PCIEPHYADR
PCIEPHYDAT
SWSM
FWSM
SW_FW_SYNC
GCR_EXT
MREVID
PICAUSE
PIENA
EICR
Name
PCIe Statistic Counter Registers
#0...#3
Function Active and Power State to Manageability
PCIe PHY Address Register
PCIe PHY Data Register
Software Semaphore Register
Firmware Semaphore Register
Software–Firmware
Synchronization
PCIe Control Extended Register
Mirrored Revision ID
PCIe Interrupt Cause
PCIe Interrupts Enable
0x00808
0x00880
0x00888
0x00810
0x00890
0x00A90+4*(n-1), n=1...2
0x00AA0+4*(n-1), n=1...2
0x00AB0+4*(n-1), n=1...2
0x00AD0+4*(n-1), n=1...2
EICS
EIMS
EIMC
EIAC
EIAM
EICS[n]
EIMS[n]
EIMC[n]
EIAM[n]
Extended Interrupt Cause
Register
Extended Interrupt Cause Set
Register
Extended Interrupt Mask Set/
Read Register
Extended Interrupt Mask Clear
Register
Extended Interrupt Auto Clear
Register
Extended Interrupt Auto Mask
Enable Register
Extended Interrupt Cause Set
Registers
Extended Interrupt Mask Set/
Read Registers
Extended Interrupt Mask Clear
Registers
Extended Interrupt Auto Mask
Enable registers
Block
PCIe
FLEEP
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
FLEEP
FLEEP
FLEEP
RW
RO
RO
RW
RO
RO
RW
RW
RW
RW
RW
RW
Interrupt RW1C
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
WO
RWS
WO
RW
RW
WO
RWS
WO
RW
Reset
Source
Page
331520-004 525
Intel
®
82599 10 GbE Controller—Device Registers — PF
Table 8-2 Register Summary (Continued)
Offset / Alias Offset Abbreviation
0x00894
0x00820+4*n, n=0...23 and
0x012300+4*(n-24), n=24...128
0x0E800+4*n, n=0...127
EITRSEL
EITR[n]
L34TIMIR[n]
Name
MSI to EITR Select
Extended Interrupt Throttle
Registers
0x0EC90
0x0EC60 / 0x05AC0
0x00900+4*n, n=0...63
0x00A00
0x00898
LLITHRESH
IMIRVP
IVAR[n]
IVAR_MISC
GPIE
L3 L4 Tuples Immediate
Interrupt Rx
LLI Size Threshold
Immediate Interrupt Rx VLAN
Priority Register
Interrupt Vector Allocation
Miscellaneous Interrupt Vector
Allocation
General Purpose Interrupt
Enable
MSI-X Table Registers
0x110C0+4*n, n=0...7 /
0x11068 [n=0]
Receive Registers
0x05080
0x05088
0x05090
0x0EA00+4*n, n=0...63 /
0x05480+4*n, n=0…15
0x05000
0x05008
0x05200+4*n, n=0...127
0x0A200+8*n, n=0...127
0x0A204+8*n, n=0...127
0x0A600+4*n, n=0...255
0x0A000+4*n, n=0...127
0x0EC80 / 0x05818
PBACL[n]
FCTRL
VLNCTRL
MCSTCTRL
PSRTYPE[n]
RXCSUM
RFCTL
MTA[n]
RAL[n]
RAH[n]
MPSAR[n]
VFTA[n]
MRQC
MSI-X PBA Clear
Filter Control Register
VLAN Control Register
Multicast Control Register
Packet Split Receive Type
Register
Receive Checksum Control
Receive Filter Control Register
Multicast Table Array
Receive Address Low
Receive Address High
MAC Pool Select Array
VLAN Filter Table Array
Multiple Receive Queues
Command Register
Block
Interrupt
Interrupt
RW
RW
RW
Reset
Source
Page
DBU-Rx
DBU-Rx
DBU-Rx
RW
RW
RW
Interrupt
Interrupt
RW
RW
Interrupt RW
PCIe
Rx-Filter
Rx-Filter
Rx-Filter
DBU-Rx
Rx-Filter
Rx-Filter
Rx-Filter
Rx-Filter
Rx-Filter
Rx-Filter
Rx-Filter
DBU-Rx
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
526 331520-004
Device Registers — PF—Intel
®
82599 10 GbE Controller
Table 8-2 Register Summary (Continued)
Offset / Alias Offset Abbreviation
0x0EC70 RQTC
RSSRK[n]
Name
RSS Queues Per Traffic Class
Register
RSS Random Key Register 0x0EB80+4*n, n=0...9 /
0x05C80+4*n, n=0...9
0x0EB00+4*n, n=0...31 /
0x05C00+4*n, n=0...31
0x0E000+4*n, n=0...127
0x0E200+4*n, n=0...127
0x0E400+4*n, n=0...127
RETA[n]
SAQF[n]
DAQF[n]
SDPQF[n]
0x0E600+4*n, n=0...127
0x0EC30
0x05128+4*n, n=0...7
0x0EC00+4*n, n=0...7
Receive DMA Registers
0x01000+0x40*n, n=0...63 and 0x0D000+0x40*(n-64), n=64...127
0x01004+0x40*n, n=0...63 and 0x0D004+0x40*(n-64), n=64...127
0x01008+0x40*n, n=0...63 and 0x0D008+0x40*(n-64), n=64...127
0x01010+0x40*n, n=0...63 and 0x0D010+0x40*(n-64), n=64...127
0x01018+0x40*n, n=0...63 and 0x0D018+0x40*(n-64), n=64...127
0x01028+0x40*n, n=0...63 and 0x0D028+0x40*(n-64), n=64...127
0x01014+0x40*n, n=0...63 and 0x0D014+0x40*(n-64), n=64...127 / 0x02100+4*n,
[n=0...15]
0x02F00
FTQF[n]
SYNQF
ETQF[n]
ETQS[n]
RDBAL[n]
RDBAH[n]
RDLEN[n]
RDH[n]
RDT[n]
RXDCTL[n]
SRRCTL[n]
RDRXCTL
Redirection Table
Block
DBU-Rx
DBU-Rx
DBU-Rx
Source Address Queue Filter
Destination Address Queue Filter
Source Destination Port Queue
Filter
Five Tuple Queue Filter
SYN Packet Queue Filter
EType Queue Filter
EType Queue Select
DBU-Rx
DBU-Rx
DBU-Rx
DBU-Rx
DBU-Rx
Rx-Filter
DBU-Rx
Receive Descriptor Base Address
Low
DMA-Rx
Receive Descriptor Base Address
High
DMA-Rx
Receive Descriptor Length
Receive Descriptor Head
Receive Descriptor Tail
Receive Descriptor Control
Split Receive Control Registers
Receive DMA Control Register
DMA-Rx
DMA-Rx
DMA-Rx
DMA-Rx
DMA-Rx
DMA-Rx
RW
RW
Reset
Source
Page
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RO
RW
RW
RW
RW
331520-004 527
Intel
®
82599 10 GbE Controller—Device Registers — PF
Table 8-2 Register Summary (Continued)
Offset / Alias Offset Abbreviation
0x03C00+4*n, n=0...7
0x03000
0x03190
0x03028
0x0102C+0x40*n, n=0...63 and 0x0D02C+0x40*(n-64), n=64...127
Transmit Registers
0x08100
RXPBSIZE[n]
RXCTRL
RXMEMWRAP
RSCDBU
RSCCTL[n]
DTXMXSZRQ
Name Block
Receive Packet Buffer Size
Receive Control Register
Rx Packet Buffer Flush Detect
RSC Data Buffer Control Register
RSC Control
DBU-Rx
DBU-Rx
DBU-Rx
DBU-Rx
DMA-Rx
DMA-Tx
0x04A80
0x04A88
0x04A8C
0x06000+0x40*n, n=0...127
0x06004+0x40*n, n=0...127
0x06008+0x40*n, n=0...127
0x06010+0x40*n, n=0...127
0x06018+0x40*n, n=0...127
0x06028+0x40*n, n=0...127
0x06038+0x40*n, n=0...127
0x0603C+0x40*n, n=0...127
0x0CC00+0x4*n, n=0...7
0x0CD10
0x08120
0x04950 +0x4*n, n=0...7
DMATXCTL
DTXTCPFLGL
DTXTCPFLGH
TDBAL[n]
TDBAH[n]
TDLEN[n]
TDH[n]
TDT[n]
TXDCTL[n]
TDWBAL[n]
TDWBAH[n]
TXPBSIZE[n]
MNGTXMAP
MTQC
TXPBTHRESH
DMA Tx TCP Max Allow Size
Requests
DMA Tx Control
DMA Tx TCP Flags Control Low
DMA Tx TCP Flags Control High
Transmit Descriptor Base
Address Low
Transmit Descriptor Base
Address High
Transmit Descriptor Length
Transmit Descriptor Head
Transmit Descriptor Tail
Transmit Descriptor Control
Tx Descriptor Completion Write
Back Address Low
Tx Descriptor Completion Write
Back Address High
Transmit Packet Buffer Size
Manageability Transmit TC
Mapping
Multiple Transmit Queues
Command Register
Tx Packet Buffer Threshold
DMA-Tx
DMA-Tx
DMA-Tx
DMA-Tx
DMA-Tx
DMA-Tx
DMA-Tx
DMA-Tx
DMA-Tx
DMA-Tx
DMA-Tx
DBU-Tx
DBU-Tx
DMA-Tx
DMA-Tx
RW
RW
RW
RW
RW
RW
RW
RO
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RO
RW
RW
Reset
Source
Page
RW
528 331520-004
Device Registers — PF—Intel
®
82599 10 GbE Controller
Table 8-2 Register Summary (Continued)
Offset / Alias Offset Abbreviation
DCB Registers
0x02430 RTRPCS
0x04900
0x0CD00
0x03020
0x0C800
0x02140+4*n, n=0...7
0x082E0+4*n, n=0...3
0x02160+4*n, n=0...7
0x04910+4*n, n=0...7
0x0CD20+4*n, n=0...7
0x0CD40+4*n, n=0...7
0x04980
0x04904
0x04908
0x0490C
0x04984
0x04988
0x0498C
RTTDCS
RTTPCS
RTRUP2TC
RTTUP2TC
RTRPT4C[n]
TXLLQ[n]
RTRPT4S[n]
RTTDT2C[n]
RTTPT2C[n]
RTTPT2S[n]
RTTBCNRM
RTTDQSEL
RTTDT1C
RTTDT1S
RTTBCNRC
RTTBCNRS
RTTBCNRD
Name
DCB Receive Packet plane
Control and Status
DCB Transmit Descriptor Plane
Control and Status
DCB Transmit Packet Plane
Control and Status
DCB Receive User Priority to
Traffic Class
DCB Transmit User Priority to
Traffic Class
DCB Receive Packet Plane T4
Config
Strict Low Latency Tx Queues
DCB Receive Packet plane T4
Status
DCB Transmit Descriptor plane
T2 Config
DCB Transmit Packet Plane T2
Config
DCB Transmit Packet Plane T2
Status
DCB Transmit Rate–Scheduler
MMW
DCB Transmit Descriptor Plane
Queue Select
DCB Transmit Descriptor Plane
T1 Config
DCB Transmit Descriptor Plane
T1 Status
DCB Transmit Rate-Scheduler
Config
DCB Transmit Rate-Scheduler
Status
DCB Transmit Rate Scheduler
Rate Drift
Block RW
Reset
Source
Page
DMA-Rx RW
DMA-Tx
DBU-Tx
DBU-Rx
DBU-Tx
RW
RW
RW
RW
DMA-Tx
DMA-Tx
DMA-Tx
DMA-Tx
DMA-Tx
DMA-Tx
DMA-Rx
DMA-Tx
DMA-Rx
DMA-Tx
RW
RW
RO
RW
DBU-Tx
DBU-Tx
DMA-Tx
RW
RO
RW
RW
RW
RO
RW
RW
RW
331520-004 529
Intel
®
82599 10 GbE Controller—Device Registers — PF
Table 8-2 Register Summary (Continued)
Offset / Alias Offset Abbreviation
DCA Registers
0x0100C+0x40*n, n=0...63 and 0x0D00C+0x40*(n-64), n=64...127 / 0x02200+4*n,
[n=0...15]
0x0600C+0x40*n, n=0...127
0x11070
DCA_RXCTRL[n]
DCA_TXCTRL[n]
DCA_ID
Name
Rx DCA Control Register
Tx DCA Control Register
DCA_CTRL
DCA Requester ID Information
Register
DCA Control Register 0x11074
Security Registers
0x08800
0x08804
0x08808
0x08810
0x08D00
0x08D04
LinkSec Registers
0x08A00
0x08F00
0x08A04
0x08F04
0x08A08
0x08A0C
0x08A10
0x08A14
0x08A18
0x08A1C+4*n, n=0...3
0x08A2C+4*n, n=0...3
0x08F08
SECTXCTRL
SECTXSTAT
SECTXBUFFAF
SECTXMINIFG
SECRXCTRL
SECRXSTAT
LSECTXCAP
LSECRXCAP
LSECTXCTRL
LSECRXCTRL
LSECTXSCL
LSECTXSCH
LSECTXSA
LSECTXPN0
LSECTXPN1
LSECTXKEY0[n]
LSECTXKEY1[n]
LSECRXSCL
Security Tx Control
Security Tx Status
Security Tx Buffer Almost Full
Security Tx Buffer Minimum IFG
Security Rx Control
Security Rx Status
LinkSec Tx Capabilities Register
LinkSec Rx Capabilities Register
LinkSec Tx Control Register
LinkSec Rx Control Register
LinkSec Tx SCI Low
LinkSec Tx SCI High
LinkSec Tx SA
LinkSec Tx SA PN 0
LinkSec Tx SA PN 1
LinkSec Tx Key 0
LinkSec Tx Key 1
LinkSec Rx SCI Low
Block
DMA-Rx
DMA-Tx
PCIe
PCIe
SEC-Tx
SEC-Tx
SEC-Tx
SEC-Tx
SEC-Rx
SEC-Rx
SEC-Tx
SEC-Rx
SEC-Tx
SEC-Rx
SEC-Tx
SEC-Tx
SEC-Tx
SEC-Tx
SEC-Tx
SEC-Tx
SEC-Tx
SEC-Rx
RW
Reset
Source
Page
RW
RW
RO
RW
RW
RW
RO
RW
RW
RW
RW
RW
RW
WO
WO
RW
RW
RO
RW
RW
RW
RO
628
629
530 331520-004
Device Registers — PF—Intel
®
82599 10 GbE Controller
Table 8-2 Register Summary (Continued)
Offset / Alias Offset Abbreviation
0x08F0C
0x08F10+4*n, n=0...1
0x08F18+4*n, n=0...1
0x08F20+0x10*n+4*m, n=0...1, m=0...3
0x08A3C
0x08A40
0x08A44
0x08A48
0x08A4C
0x08F40
0x08F44
0x08F48
0x08F4C
0x08F50
0x08F54
0x08F58
0x08F5C
0x08F60
0x08F64+4*n, n=0...1
0x08F6C+4*n, n=0...1
0x08F74+4*n, n=0...1
0x08F7C
0x08F80
IPsec Registers
0x08900
0x08908+4*n, n=0...3
LSECRXSCH
LSECRXSA[n]
LSECRXPN[n]
LSECRXKEY[n,m]
Name
LinkSec Rx SCI High
LinkSec Rx SA
LinkSec Rx SA PN
LinkSec Rx Key
LSECTXUT
LSECTXPKTE
LSECTXPKTP
LSECTXOCTE
LSECTXOCTP
LSECRXUT
LSECRXOCTE
LSECRXOCTP
LSECRXBAD
LSECRXNOSCI
LSECRXUNSCI
LSECRXUC
LSECRXDELAY
LSECRXLATE
LSECRXOK[n]
LSECRXINV[n]
LSECRXNV[n]
LSECRXUNSA
LSECRXNUSA
IPSTXIDX
IPSTXKEY[n]
IPsec Tx Index
IPsec Tx Key Registers
Tx Untagged Packet Counter
Encrypted Tx Packets
Protected Tx Packets
Encrypted Tx Octets
Protected Tx Octets
LinkSec Untagged Rx Packet
LinkSec Rx Octets Decrypted
LinkSec Rx Octets Validated
LinkSec Rx Packet with Bad Tag
LinkSec No SCI
LinkSec Unknown SCI
LinkSec Rx Unchecked Packets
LinkSec Rx Delayed Packets
LinkSec Rx Late Packets
LinkSec Rx Packet OK
LinkSec Rx Invalid
LinkSec Rx Not Valid
LinkSec Rx Unused SA
LinkSec Rx Not Using SA
SEC-Rx
SEC-Rx
SEC-Rx
SEC-Rx
SEC-Rx
SEC-Rx
SEC-Rx
SEC-Rx
SEC-Tx
SEC-Tx
SEC-Tx
SEC-Tx
SEC-Tx
SEC-Rx
SEC-Rx
SEC-Rx
SEC-Rx
SEC-Rx
SEC-Rx
SEC-Tx
SEC-Tx
Block
SEC-Rx
SEC-Rx
SEC-Rx
SEC-Rx
RO
RO
RO
RO
RO
RO
RO
RO
RO
RC
RC
RC
RO
RO
RO
RO
RO
RO
RO
RW
RW
RW
RW
WO
Reset
Source
Page
RW
RW
331520-004 531
Intel
®
82599 10 GbE Controller—Device Registers — PF
Table 8-2 Register Summary (Continued)
Offset / Alias Offset Abbreviation
0x08904
0x08E00
0x08E04+4*n, n=[0...3]
0x08E14
0x08E18
0x08E1C+4*n, n=0...3
0x08E2C
0x08E30
Timers Registers
0x0004C
FCoE Registers
0x05100
0x0ED00
0x0ED10+4*n, n=0...7
0x02410
0x02414
0x02418
0x02420
0x05108
0x051D8
0x05110
Flow Director Registers
Global Settings Registers
0x0EE00
0x0EE68
0x0EE6C
TCPTIMER
FCRXCTRL
FCRECTL
FCRETA[n]
FCPTRL
FCPTRH
FCBUFF
FCDMARW
FCFLT
FCPARAM
FCFLTRW
IPSTXSALT
IPSRXIDX
IPSRXIPADDR
IPSRXSPI
IPSRXIPIDX
IPSRXKEY[n]
IPSRXSALT
IPSRXMOD
FDIRCTRL
FDIRHKEY
FDIRSKEY
Name
IPsec Tx Salt Register
IPsec Rx Index
IPsec Rx IP address Register
IPsec Rx SPI Register
IPsec Rx SPI Register
IPsec Rx Key Register
IPsec Rx Salt Register
IPsec Rx Mode Register
TCP Timer
FC Receive Control
FCoE Redirection Control
FCoE Redirection Table
FC User Descriptor PTR Low
FC User Descriptor PTR High
FC Buffer Control
FC Receive DMA RW
FC FLT Context
FC Offset Parameter
FC Filter RW Control
Flow Director Filters Control
Register
Flow Director Filters Lookup
Table Hash Key
Flow Director Filters Signature
Hash Key
Block
SEC-Tx
SEC-Rx
SEC-Rx
SEC-Rx
SEC-Rx
SEC-Rx
SEC-Rx
SEC-Rx
Target RW
Rx-Filter
DBU-Rx
DBU-Rx
DMA-Rx
DMA-Rx
DMA-Rx
DMA-Rx
Rx-Filter
Rx-Filter
Rx-Filter
RW
RW
RW
RW
RW
RW
RW
RW
RW
WO
DBU-Rx
DBU-Rx
DBU-Rx
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Reset
Source
Page
532 331520-004
Device Registers — PF—Intel
®
82599 10 GbE Controller
Table 8-2 Register Summary (Continued)
Offset / Alias Offset Abbreviation
0x0EE3C
0x0EE40
0x0EE44
0x0EE48
0x0EE74
FDIRTCPM
FDIRUDPM
FDIRIP6M
0x0EE70 FDIRM
Global Status / Statistics Registers
0x0EE38 FDIRFREE
0x0EE4C
0x0EE50
FDIRLEN
FDIRUSTAT
0x0EE54
0x0EE58
0x0EE5C
FDIRDIP4M
FDIRSIP4M
FDIRFSTAT
FDIRMATCH
FDIRMISS
Name Block
Flow Director Filters IPv4 Mask
Flow Director Filters Source IPv4
Mask
Flow Director Filters TCP Mask
Flow Director Filters UDP Mask
Flow Director Filters IPv6 Mask
Flow Director Filters Other Mask
DBU-Rx
DBU-Rx
DBU-Rx
DBU-Rx
DBU-Rx
DBU-Rx
Flow Director Filters Free
Flow Director Filters Length
Flow Director Filters Usage
Statistics
Flow Director Filters Failed Usage
Statistics
Flow Director Filters Match
Statistics
Flow Director Filters Miss Match
Statistics
DBU-Rx RW
DBU-Rx
DBU-Rx
RC
RW / RC
DBU-Rx RW / RC
DBU-Rx
DBU-Rx
RC
RC
RW
RW
RW
RW
RW
RW
RW
Reset
Source
Page
Flow Programming Registers
0x0EE0C+4*n, n=0…2 FDIRSIPv6[n]
0x0EE18
0x0EE1C
FDIRIPSA
FDIRIPDA
0x0EE20
0x0EE24
FDIRPORT
FDIRVLAN
0x0EE28
0x0EE2C
FDIRHASH
FDIRCMD
Flow Director Filters Source IPv6
Flow Director Filters IP SA
Flow Director Filters IP DA
Flow Director Filters Port
Flow Director Filters VLAN and
FLEX bytes
Flow Director Filters Hash
Signature
Flow Director Filters Command
Register
DBU-Rx
DBU-Rx
DBU-Rx
DBU-Rx
DBU-Rx
DBU-Rx
DBU-Rx
RW
RW
RW
RW
RW
RW
RW
MAC Registers
0x04200
0x04208
PCS1GCFIG
PCS1GLCTL
PCS_1G Global Config Register 1
PCG_1G link Control Register
MAC
MAC
RW
RW
331520-004 533
Intel
®
82599 10 GbE Controller—Device Registers — PF
Table 8-2 Register Summary (Continued)
Offset / Alias Offset Abbreviation
0x0420C
0x04218
0x0421C
0x04220
0x04224
0x04240
0x04244
0x04248
0x0425C
0x04260
0x04268
0x4288
0x0428C
0x04290
0x04298
0x0429C
0x042A0
0x042A4
0x04324
0x042A8
0x042B0
0x042B4
PCS1GLSTA
PCS1GANA
PCS1GANLP
PCS1GANNP
PCS1GANLPNP
HLREG0
HLREG1
PAP
MSCA
MSRWD
MAXFRS
PCSS1
PCSS2
XPCSS
SERDESC
MACS
AUTOC
LINKS
LINKS2
AUTOC2
ANLP1
ANLP2
Name
PCS_1G Link Status Register
PCS_1 Gb/s Auto-Negotiation
Advanced Register
PCS_1GAN LP Ability Register
PCS_1G Auto-Negotiation Next
Page Transmit Register
PCS_1G Auto-Negotiation LP's
Next Page Register
MAC Core Control 0 Register
MAC Core Status 1 Register
Pause and Pace Register
MDI Single Command and
Address
MDI Single Read and Write Data
Max Frame Size
XGXS Status 1
XGXS Status 2
10GBASE-X PCS Status
SerDes Interface Control
Register
FIFO Status/CNTL report
Register
Auto-Negotiation Control
Register
Link Status Register
Link Status Register 2
Auto-Negotiation Control 2
Register
Auto-Negotiation Link Partner
Link Control Word 1 Register
Auto-Negotiation Link Partner
Link Control Word 2 Register
Block
MAC
MAC
MAC
MAC
MAC
MAC
MAC
MAC
MAC
MAC
MAC
MAC
MAC
MAC
MAC
MAC
MAC
MAC
MAC
MAC
MAC
MAC
RW
RO
RO
RW
RO
RO
RO
RW
RO
RW
RO
RW
RW
RW
RW
RO
RO
RO
RW
RW
RW
RO
RW
Reset
Source
Page
534 331520-004
Device Registers — PF—Intel
®
82599 10 GbE Controller
Table 8-2 Register Summary (Continued)
Offset / Alias Offset Abbreviation
0x042D0
0x042D4
0x042D8
0x042E0
0x042E4
0x042E8
0x042EC
0x014F00
0x014F10
MMNGC
ANLPNP1
ANLPNP2
KRPCSFC
KRPCSS
FECS1
FECS2
CoreCTL
SMADARCTL
MFLCN
SGMIIC
Name
MAC Manageability Control
Register
Auto-Negotiation Link Partner
Next Page 1 register
Auto-Negotiation Link Partner
Next Page 2 register
KR PCS and FEC Control Register
KR PCS Status Register
FEC Status 1 Register
FEC Status 2 Register
Core Analog Configuration
Register
Core Common Configuration
Register
MAC Flow Control Register
SGMII Control Register
0x04294
0x04314
Statistic Registers
0x04000
0x04004
0x04008
0x04034
0x04038
0x04040
0x08780
0x041A4
0x041A8
0x04140+4*n, n=0...7
0x04160+4*n, n=0...7
0x0405C
CRCERRS
ILLERRC
ERRBC
MLFC
MRFC
RLEC
SSVPC
LXONRXCNT
LXOFFRXCNT
PXONRXCNT[n]
PXOFFRXCNT[n]
PRC64
CRC Error Count
Illegal Byte Error Count
Error Byte Count
MAC Local Fault Count
MAC Remote Fault Count
Receive Length Error Count
Switch Security Violation Packet
Count
Link XON Received Count
Link XOFF Received Count
Priority XON Received Count
Priority XOFF Received Count
Packets Received [64 Bytes]
Count
Block
MAC
MAC
MAC
MAC
MAC
MAC
MAC
MAC
MAC
MAC
MAC
STAT
STAT
STAT
STAT
STAT
STAT
STAT
STAT
STAT
STAT
STAT
DMA-Tx
RC
RC
RC
RC
RW
RC
RC
RC
RC
RC
RC
RC
RW
RO
Reset
Source
Page
RO
RO
RW
RO
RC
RC
RW
RW
RW
RW
331520-004 535
Intel
®
82599 10 GbE Controller—Device Registers — PF
Table 8-2 Register Summary (Continued)
Offset / Alias Offset Abbreviation
0x04060
0x04064
0x04068
0x0406C
0x04070
0x04078
0x0407C
0x04074
0x04088
0x0408C
0x041B0
0x041B4
0x041B8
0x02F50
0x02F54
0x02F58
0x02F5C
0x02F60
0x02F64
0x02F68
PRC127
PRC255
PRC511
PRC1023
PRC1522
BPRC
MPRC
GPRC
GORCL
GORCH
RXNFGPC
RXNFGBCL
RXNFGBCH
RXDGPC
RXDGBCL
RXDGBCH
RXDDPC
RXDDBCL
RXDDBCH
RXLPBKPC
Name Block
Packets Received [65–127
Bytes] Count
Packets Received [128–255
Bytes] Count
Packets Received [256–511
Bytes] Count
Packets Received [512–1023
Bytes] Count
Packets Received [1024 to Max
Bytes] Count
Broadcast Packets Received
Count
Multicast Packets Received
Count
Good Packets Received Count
Good Octets Received Count Low
Good Octets Received Count
High
Good Rx Non-Filtered Packet
Counter
Good Rx Non-Filter Byte Counter
Low
Good Rx Non-Filter Byte Counter
High
DMA Good Rx Packet Counter
DMA Good Rx Byte Counter Low
DMA Good Rx Byte Counter High
DMA Duplicated Good Rx Packet
Counter
DMA Duplicated Good Rx Byte
Counter Low
DMA Duplicated Good Rx Byte
Counter High
DMA Good Rx LPBK Packet
Counter
STAT
STAT
STAT
STAT
STAT
STAT
STAT
STAT
STAT
STAT
STAT
STAT
STAT
DMA-Rx
DMA-Rx
DMA-Rx
DMA-Rx
DMA-Rx
DMA-Rx
DMA-Rx
RW
RW
Reset
Source
Page
RW
RW
RW
RW
RC
RC
RC
RC
RC
RC
RC
RC
RC
RC
RC
RC
RC
RC
RC
536 331520-004
Device Registers — PF—Intel
®
82599 10 GbE Controller
Table 8-2 Register Summary (Continued)
Offset / Alias Offset Abbreviation
0x02F6C
0x02F70
0x02F74
0x02F78
0x02F7C
0x04080
0x04090
0x04094
0x087A0
0x087A4
0x087A8
0x040A4
0x040A8
0x040AC
0x040B0
0x040B4
0x040B8
0x040C0
0x040C4
0x040D0
0x040D4
0x040D8
RXLPBKBCL
RXLPBKBCH
RXDLPBKPC
RXDLPBKBCL
RXDLPBKBCH
GPTC
GOTCL
GOTCH
TXDGPC
TXDGBCL
TXDGBCH
RUC
RFC
ROC
RJC
MNGPRC
MNGPDC
TORL
TORH
TPR
TPT
PTC64
Name Block
DMA Good Rx LPBK Byte Counter
Low
DMA Good Rx LPBK Byte Counter
High
DMA Duplicated Good Rx LPBK
Packet Counter
DMA Duplicated Good Rx LPBK
Byte Counter Low
DMA Duplicated Good Rx LPBK
Byte Counter High
Good Packets Transmitted Count
Good Octets Transmitted Count
Low
Good Octets Transmitted Count
High
DMA Good Tx Packet Counter
DMA Good Tx Byte Counter Low
DMA Good Tx Byte Counter High
Receive Undersize Count
Receive Fragment Count
Receive Oversize Count
Receive Jabber Count
Management Packets Received
Count
Management Packets Dropped
Count
Total Octets Received
Total Octets Received
Total Packets Received
Total Packets Transmitted
Packets Transmitted (64 Bytes)
Count
DMA-Rx
DMA-Rx
DMA-Rx
DMA-Rx
DMA-Rx
STAT
STAT
STAT
STAT
STAT
STAT
STAT
STAT
STAT
DMA-Tx
DMA-Tx
DMA-Tx
STAT
STAT
STAT
STAT
STAT
RW
RC
Reset
Source
Page
RC
RC
RC
RC
RC
RC
RC
RO
RC
RC
RC
RO
RC
RO
RC
RC
RC
RC
RC
RC
RC
331520-004 537
Intel
®
82599 10 GbE Controller—Device Registers — PF
Table 8-2 Register Summary (Continued)
Offset / Alias Offset Abbreviation
0x040DC
0x040E0
0x040E4
0x040E8
0x040EC
0x040F0
0x040F4
0x04010
0x04120
0x02300+4*n, n=0...31
0x02F40
0x08600+4*n, n=0...31 /
0x07300+4*n, n=0…7
0x01030+0x40*n, n=0...15
0x01430+0x40*n, n=0...15
RXDSTATCTRL
TQSM[n]
QPRC[n]
QPRDC[n]
0x1034+0x40*n, n=0...15
0x1038+0x40*n, n=0...15
0x08680+0x4*n, n=0...15 /
0x06030+0x40*n, n=0...15
0x08700+0x8*n, n=0...15
QPTC
QBTC_L[n]
0x08704+0x8*n, n=0...15
0x05118
0x0241C
PTC127
PTC255
PTC511
PTC1023
PTC1522
MPTC
BPTC
MSPDC
XEC
RQSMR[n]
QBRC_L[n]
QBRC_H[n]
QBTC_H[n]
FCCRC
FCOERPDC
Name Block
Packets Transmitted [65–127
Bytes] Count
Packets Transmitted [128–255
Bytes] Count
Packets Transmitted [256–511
Bytes] Count
Packets Transmitted [512–1023
Bytes] Count
Packets Transmitted [Greater than 1024 Bytes] Count
Multicast Packets Transmitted
Count
Broadcast Packets Transmitted
Count
MAC short Packet Discard Count
XSUM Error Count
Receive Queue Statistic Mapping
Registers
Rx DMA Statistic Counter Control
Transmit Queue Statistic
Mapping Registers
Queue Packets Received Count
Queue Packets Received Drop
Count
Queue Bytes Received Count
Low
Queue Bytes Received Count
High
Queue Packets Transmitted
Count
Queue Bytes Transmitted Count
Low
Queue Bytes Transmitted Count
High
FC CRC Error Count
FCoE Rx Packets Dropped Count
STAT
STAT
STAT
STAT
STAT
STAT
STAT
STAT
STAT
DMA-Rx
DMA-Tx
DMA-Tx
DMA-Rx
DMA-Rx
DMA-Rx
DMA-Rx
DMA-Tx
DMA-Tx
DMA-Tx
Rx-Filter
DMA-Rx
RW
RC
Reset
Source
Page
RC
RC
RC
RC
RC
RC
RC
RC
RW
RW
RW
RC
RC
RC
RC
RC
RC
RC
RC
RC
538 331520-004
Device Registers — PF—Intel
®
82599 10 GbE Controller
Table 8-2 Register Summary (Continued)
Offset / Alias Offset Abbreviation
0x02424
0x02428
0x0242C
0x08784
FCLAST
FCOEPRC
FCOEDWRC
FCOEPTC
0x08788
Wake-Up Control Registers
0x05800
0x05808
FCOEDWTC
WUC
WUFC
0x5838
0x05840+8*n, n = 0...3
0x05880+4*n, n = 0...3
0x05900
0x05A00+4*n, n=0...31
IPAV
IP4AT[n]
IP6AT[n]
WUPL
WUPM[n]
Name
FC Last Error Count
FCoE Packets Received Count
FCOE DWord Received Count
FCoE Packets Transmitted Count
FCoE DWord Transmitted Count
Wake Up Control Register
Wake Up Filter Control Register
IP Address Valid
IPv4 Address Table
IPv6 Address Table
Wake Up Packet Length
Wake Up Packet Memory (128
Bytes)
Flexible Host Filter Table registers
0x09000 — 0x093FC,
0x09800 — 0x099FC
Management Filters Registers
FHFT
0x5010 +4*n, n=0...7
MAVTV[n]
0x5030+4*n, n=0...7
0x05190+4*n, n=0...3
MFUTP[n]
METF[n]
0x05820
0x5824
0x5860
0x5890+4*n, n=0...7
0x05160+4*n, n=0...7
0x58B0+0x10*m+4*n, m=0...3, n=0...3
MANC
MFVAL
MANC2H
MDEF[n]
MDEF_EXT[n]
MIPAF
Block
DMA-Rx
DMA-Rx
DMA-Rx
DMA-Tx
DMA-Tx
Rx-Filter
Management VLAN TAG Value
Management Flex UDP/TCP Ports
Management Ethernet Type
Filters
Management Control Register
Manageability Filters Valid
Management Control To Host
Register
Manageability Decision Filters
Manageability Decision Filters
Manageability IP Address Filter
Rx-Filter
Rx-Filter
Rx-Filter
Rx-Filter
Rx-Filter
Rx-Filter
Rx-Filter
Rx-Filter
Rx-Filter
Rx-Filter
Rx-Filter
Rx-Filter
Rx-Filter
Rx-Filter
Rx-Filter
Rx-Filter
RW
RO
RO
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RC
RC
RC
RC
RC
Reset
Source
Page
331520-004 539
Intel
®
82599 10 GbE Controller—Device Registers — PF
Table 8-2 Register Summary (Continued)
Offset / Alias Offset Abbreviation
0x5910+8*n, n=0...3
0x5914+8*n, n=0...3
0x09400-0x097FC
MMAL[n]
MMAH[n]
FTFT
Name
Manageability Ethernet MAC
Address Low
Manageability Ethernet MAC
Address High
Flexible TCO Filter Table registers
LinkSec SW/FW Interface
0x05120
0x08C00
0x08C04
0x08C08
0x08C0C
0x08C10
0x08C14
0x08C18
0x015F14 LSWFW
Time Sync (IEEE 1588) Registers
0x05188 TSYNCRXCTL
0x051E8
0x051A4
0x051A0
0x051A8
RXSTMPL
RXSTMPH
RXSATRL
RXSATRH
RXMTRL
TSYNCTXCTL
TXSTMPL
TXSTMPH
SYSTIML
SYSTIMH
TIMINCA
TIMADJL
0x08C1C
0x08C20
0x08C24
0x08C28
0x08C2C
0x08C30
TIMADJH
TSAUXC
TRGTTIML0
TRGTTIMH0
TRGTTIML1
TRGTTIMH1
Block
Rx-Filter
Rx-Filter
Rx-Filter
MNG
Rx Time Sync Control Register
Rx Timestamp Low
Rx Timestamp High
Rx Timestamp Attributes Low
Rx Timestamp Attributes High
Rx Message Type Register Low
Tx Time Sync Control Register
Tx Timestamp Value Low
Tx Timestamp Value High
System Time Register Low
System Time Register High
Increment Attributes Register
Time Adjustment Offset Register low
Time Adjustment Offset Register
High
TimeSync Auxiliary Control
Register
Target Time Register 0 Low
Target Time Register 0 High
Target Time Register 1 Low
Target Time Register 1 High
SEC-Tx
SEC-Tx
SEC-Tx
SEC-Tx
SEC-Tx
SEC-Tx
Rx-Filter
Rx-Filter
Rx-Filter
Rx-Filter
Rx-Filter
Rx-Filter
SEC-Tx
SEC-Tx
SEC-Tx
SEC-Tx
SEC-Tx
SEC-Tx
SEC-Tx
RW
RW
Reset
Source
Page
RW
RW
RO
RO
RO
RW
RW
RW
RW
RO
RO
RW
RW
RW
RO
RO
RW
RW
RW
RW
RW
RW
540 331520-004
Device Registers — PF—Intel
®
82599 10 GbE Controller
Table 8-2 Register Summary (Continued)
Offset / Alias Offset Abbreviation
0x08C3C
0x08C40
0x08C44
0x08C48
AUXSTMPL0
AUXSTMPH0
AUXSTMPL1
AUXSTMPH1
Name
Auxiliary Time Stamp 0 Register low
Auxiliary Time Stamp 0 Register high
Auxiliary Time Stamp 1 Register low
Auxiliary Time Stamp 1 Register high
Virtualization PF Registers
0x051B0
0x04B00+4*n, n=0...63
0x00710+4*n, n=0...3
PFVTCTL
PFMailbox[n]
PFMBICR[n]
0x00720+4*n, n=0...1
0x00600, 0x001C0
0x00700+4*n, n=0...1
0x051E0+4*n, n=0...1
0x08110+4*n, n=0...1
0x02F04
0x05180+4 *n, n=0...1
0x08200+4*n, n=0...7
0x08220
0x08000+4*n, n=0...63
0x0F000+4*n, n=0...63
0x0F100+4*n, n=0...63
0x0F200+4*n, n=0...127
0x0F400+4*n, n=0...127
0x0F600+4*n, n= 0...3
PFMBIMR[n]
PFVFLRE[n]
PFVFLREC[n]
PFVFRE[n]
PFVFTE[n]
PFQDE
PFVMTXSW[n]
PFVFSPOOF[n]
PFDTXGSWC
PFVMVIR[n]
PFVML2FLT[n]
PFVLVF[n]
PFVLVFB[n]
PFUTA[n]
PFMRCTL[n]
PF Virtual Control Register
PF Mailbox
PF Mailbox Interrupt Causes
Register
PF Mailbox Interrupt Mask
Register
PF VFLR Events Indication
PF VFLR Events Clear
PF VF Receive Enable
PF VF Transmit Enable
PF Queue Drop Enable Register
PF VM Tx Switch Loopback
Enable
PF VF Anti Spoof Control
PF DMA Tx General Switch
Control
PF VM VLAN Insert Register
PF VM L2 Control Register
PF VM VLAN Pool Filter
PF VM VLAN Pool Filter Bitmap
PF Unicast Table Array
PF Mirror Rule Control
Block
SEC-Tx
SEC-Tx
SEC-Tx
SEC-Tx
RW
RO
Rx-Filter
Target
Target
RW
RW
RW1C
Target
Target
Target
DMA-Tx
DMA-Rx
Rx-Filter
DMA-Tx
DMA-Tx
DMA-Tx
Rx-Filter
Rx-Filter
Rx-Filter
Rx-Filter
Rx-Filter
RO
RO
RO
RW
RW
RW
RW
RO
W1C
RW
RW
RW
RW
RW
RW
RW
RW
RW
Reset
Source
Page
331520-004 541
Intel
®
82599 10 GbE Controller—Device Registers — PF
Table 8-2 Register Summary (Continued)
Offset / Alias Offset Abbreviation
0x0F610+4*n, n= 0...7
0x0F630+4*n, n= 0...7
PFMRVLAN[n]
PFMRVM[n]
Name
PF Mirror Rule VLAN
PF Mirror Rule Pool
Note:
Block
Rx-Filter
Rx-Filter
RW
RW
RW
Reset
Source
Page
(*) The MAC Manageability Control Register is read only to the host and read/write to manageability.
542 331520-004
advertisement
Key Features
- Dual Port 10 GbE
- Single port Device
- Serial Flash Interface
- 4-wire SPI EEPROM Interface
- Configurable LED Operation
- Protected EEPROM space
- Jumbo frames(up to 15.5 KB)
- Flow control support
- TCP segmentation offload (up to 256 KB)
- IPv6 support
Related manuals
Frequently Answers and Questions
What type of interface does the Intel 82599 10 GbE Controller use?
What is the maximum jumbo frame size supported by the Intel 82599 10 GbE Controller?
Does the Intel 82599 10 GbE Controller support IPv6?
advertisement