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Intel
®
82599 10 GbE Controller—PCI-Express* (PCIe*)
• PM_Enter_L1
• PM_Enter_L23
• InitFC1-P
• InitFC1-NP
• InitFC1-Cpl
• InitFC2-P
• InitFC2-NP
• InitFC2-Cpl
• UpdateFC-P
• UpdateFC-NP
Note:
UpdateFC-Cpl is not sent because of the infinite FC-Cpl allocation.
3.1.5.3 Transmit EDB Nullifying (End Bad)
If retrain is necessary, there is a need to guarantee that no abrupt termination of the Tx packet happens. For this reason, early termination of the transmitted packet is possible.
This is done by appending the EDB to the packet.
3.1.6 Physical Layer
3.1.6.1 Link Speed
The 82599 supports PCIe V2.0 (2.5GT/s or 5GT/s). The following configuration controls link speed:
• PCIe
Supported Link Speeds
bit — Indicates the link speeds supported by the 82599.
Loaded from the PCIe
Link Speed
field in the EEPROM.
EEPROM Word Offset
(Starting at Odd
Word)
Allow PCIe
V2.0(Default)
2*N+1 0x094
2*N+2 0x0000
Force PCIe
V2.0 Setting
0x0100
Description
MORIA6 register offset (lower word).
Disabling PCIe V2.0 is controlled by setting bit[8] in this register.
When the bit is set the 82599 does not advertise PCIe V2.0 linkspeed support.
• PCIe
Current Link Speed
bit — Indicates the negotiated Link speed.
• PCIe
Target Link Speed
bit — used to set the target compliance mode speed when software is using the
Enter Compliance
bit to force a link into compliance mode. The default value is the highest link speed supported defined by the previous
Supported
Link Speeds
.
76 331520-004
PCI-Express* (PCIe*)—Intel
®
82599 10 GbE Controller
The 82599 does not initiate a hardware autonomous speed change.
The 82599 supports entering compliance mode at the speed indicated in the
Target Link
Speed
field in the PCIe Link Control 2 register. Compliance mode functionality is controlled via the PCIe Link Control 2 register.
3.1.6.2 Link Width
• The 82599 supports a maximum link width of x8, x4, x2, or x1 as determined by the
PCIe Analog Configuration Module in the EEPROM and can be set as follows. Note that these settings might not be needed during normal operation:
EEPROM Word Offset
(Starting at Odd
Word)
Enable x8
Setting
(Default)
Limit to x4
Setting
Limit to x2
Setting
Limit to x1
Setting
2*N+1 0x094
Description
MORIA6 register offset (lower word).
2*N+2 0x0000 0x00F0 0x00FC 0x00FE Lanes can be disabled by setting bits[7:0] in this offset. Having bit[X] set causes laneX to be disabled, resulting in narrower link widths (bits per lane).
The maximum link width is loaded into the
Max Link Width
field of the PCIe Capability register (LCAP[11:6]). Hardware default is the x8 link.
During link configuration, the platform and the 82599 negotiate on a common link width.
The link width must be one of the supported PCIe link widths (x1, 2x, x4, x8), such that:
• If Maximum Link Width = x8, then the 82599 negotiates to either x8, x4, x2 or x1
1
• If Maximum Link Width = x4, then the 82599 negotiates to either x4 or x1
• If Maximum Link Width = x1, then the 82599 only negotiates to x1
The 82599 does not initiate a hardware autonomous link width change.
Note:
Some PCIe x8 slots are actually configured as x4 slots. These slots have insufficient bandwidth for full 10 GbE line rate with dual port 10 GbE devices. If a solution suffers bandwidth issues when both 10 GbE ports are active, it is recommended to verify that the PCIe slot is indeed a true PCIe x8.
3.1.6.3 Polarity Inversion
If polarity inversion is detected, the receiver must invert the received data.
During the training sequence, the receiver looks at symbols 6-15 of TS1 and TS2 as the indicators of lane polarity inversion (D+ and D- are swapped). If lane polarity inversion occurs, the TS1 symbols 6-15 received are D21.5 as opposed to the expected D10.2.
Similarly, if lane polarity inversion occurs, symbols 6-15 of the TS2 ordered set are D26.5 as opposed to the expected 5 D5.2. This provides the clear indication of lane polarity inversion.
1. See restriction in
.
331520-004 77
Intel
®
82599 10 GbE Controller—PCI-Express* (PCIe*)
3.1.6.4 L0s Exit Latency
The number of FTS sequences (N_FTS) sent during L0s exit is loaded from the EEPROM into an 8-bit read-only register.
3.1.6.5 Lane-to-Lane De-Skew
A multi-lane link can have many sources of lane-to-lane skew. Although symbols are transmitted simultaneously on all lanes, they cannot be expected to arrive at the receiver without lane-to-lane skew. The lane-to-lane skew can include components, which are less than one bit time, bit time units (400/200 ps for 2.5/5 Gb), or full symbol time units (4/2 ns). This type of skew is caused by the retiming repeaters' insert/delete operations.
Receivers use TS1 or TS2 or Skip Ordered Sets (SOS) to perform link de-skew functions.
The 82599 supports de-skew of up to 12 symbols time [48 ns for PCIe v2.0 (2.5GT/s) and 24 ns for PCIe V2.0 (5GT/s)].
3.1.6.6 Lane Reversal
Auto lane reversal is supported by the 82599 at its hardware default setting. The following lane reversal modes are supported:
• Lane configurations x8, x4, x2, and x1
• Lane reversal in x8 and in x4
• Degraded mode (downshift) from x8 to x4 to x2 to x1 and from x4 to x1, with one restriction — if lane reversal is executed in x8, then downshift is only to x1 and not to x4.
Figure 3-2 through Figure 3-5 shows the lane downshift in both regular and reversal connections as well as lane connectivity from a system level perspective.
Root
Complex
Root
Complex
Root
Complex
Downgrade to x4
Ethernet
Controller
Ethernet
Controller
Figure 3-2 Lane Downshift in an x8 Configuration
Downgrade to x1
Ethernet
Controller
78 331520-004
PCI-Express* (PCIe*)—Intel
®
82599 10 GbE Controller
Root
Complex
Root
Complex
Downgrade to x1
Ethernet
Controller
Ethernet
Controller
Figure 3-3 Lane Downshift in a Reversal x8 Configuration
Downgrade to x1
Ethernet Controller
Figure 3-4 Lane Downshift in a x4 Configuration
Ethernet Controller
Downgrade to x1
Ethernet Controller Ethernet Controller
Figure 3-5 Lane Downshift in an x4 Reversal Configuration
331520-004 79
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