Intel 82599 10 GbE Controller Datasheet ®

Pin Assignment—Intel

®

82599 10 GbE Controller

See AC specifications in

Section 11.4.2.1

.

2.1.13 Miscellaneous

Reserved Pin Name

LAN_PWR_GOOD

Ball #

A14

POR_BYPASS

RSVDAC6_VCC

D19

AC6

Type

In

Pu

In

Pu

Name and Function

LAN Power Good. A 3.3V input signal. A transition from low to high initializes the 82599 into operation. If not used (POR_BYPASS = 0b), an internal Power-on-Reset

(POR) circuit triggers the 82599 power-up.

Bypass indication as to whether or not to use the internal

POR or the LAN_PWR_GOOD pin. When set to 1b, the

82599 disables the internal POR circuit and uses the

LAN_PWR_GOOD pin as a POR indication.

This input requires an external pull up. See the product’s

Schematic Checklist for detail.

OSC_SEL

AUX_PWR

MAIN_PWR_OK

LAN1_DIS_N

LAN0_DIS_N

AA9

AB9

AC9

AD20

AD21

In

T/s

Pu

T/s

Pu

T/s

T/s

Pu

Defines the input clock connected to the REFCLKIN_p/

REFCLKIN_n pins:

0b

1b

XTAL Clock (valid only for 25 MHz)

OSC Clock

This pin is a strapping option latched at LAN_PWR_GOOD.

Auxiliary Power Available. When set, indicates that auxiliary power is available and the 82599 should support

D3

COLD

power state if enabled to do so. This pin is latched at the rising edge of LAN_PWR_GOOD.

Main Power OK. Indicates that platform main power is up.

Must be connected externally.

This pin is a strapping pin latched at the rising edge of

LAN_PWR_GOOD. If this pin is not connected or driven high during initialization, LAN 1 is enabled. If this pin is driven low during initialization, LAN 1 port is disabled.

This pin is a strapping option pin latched at the rising edge of LAN_PWR_GOOD. If this pin is not connected or driven high during initialization, LAN 0 is enabled. If this pin is driven low during initialization, LAN 0 port is disabled.

When LAN 0 port is disabled MNG is not functional and it must not be enabled in the EEPROM Control Word 1.

331520-004 53