ST7LITEU05 ST7LITEU09 Interrupts
External interrupt vectors can be loaded into the PC register if the corresponding external interrupt occurred and if the I bit is cleared. These interrupts allow the processor to leave the
Halt low-power mode.
The external interrupt polarity is selected through the miscellaneous register or interrupt register (if available).
An external interrupt triggered on edge is latched and the interrupt request automatically cleared upon entering the interrupt service routine.
Caution: The type of sensitivity defined in the Miscellaneous or Interrupt register (if available) applies to the ei source. In case of a NANDed source (as described in the I/O ports section), a low level on an I/O pin, configured as input with interrupt, masks the interrupt request even in case of rising-edge sensitivity.
Note:
Different peripheral interrupt flags in the status register are able to cause an interrupt when they are active if both:
• The I bit of the CC register is cleared.
• The corresponding enable bit is set in the control register.
If any of these two conditions is false, the interrupt is latched and thus remains pending.
Clearing an interrupt request is done by:
• Writing “0” to the corresponding bit in the status register or
• Access to the status register while the flag is set followed by a read or write of an associated register.
The clearing sequence resets the internal latch. A pending interrupt (that is, waiting for being enabled) is therefore lost if the clear sequence is executed.
Figure 18. Interrupt processing flowchart
FROM RESET
N
I BIT SET?
Y N INTERRUPT
PENDING?
FETCH NEXT INSTRUCTION
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N
IRET?
Y
STACK PC, X, A, CC
SET I BIT
Y
LOAD PC FROM INTERRUPT VECTOR
EXECUTE INSTRUCTION
RESTORE PC, X, A, CC FROM STACK
THIS CLEARS I BIT BY DEFAULT
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Interrupts ST7LITEU05 ST7LITEU09
Table 9. Interrupt mapping
N°
Source block
Description
Register label
Priority order
Exit from
Halt
Address vector
4
5
6
3)
7
0
1
-
-
2
3
2)
8
9
10
11
12
13
RESET
TRAP
AWU ei0 ei1 ei2
-
-
-
(2) ei3 ei4
(3)
SI
AT TIMER
LITE TIMER
Reset
Software interrupt
Auto Wakeup interrupt
External interrupt 0
External interrupt 1
External interrupt 2
(2)
Not used
External interrupt 3
External interrupt 4
(3)
AVD interrupt
AT TIMER output compare interrupt
AT TIMER overflow Interrupt
LITE TIMER input capture interrupt
LITE TIMER RTC1 interrupt
Not used
Not used
N/A
AWUCSR
N/A
SICSR
PWMxCSR or ATCSR
ATCSR
LTCSR
LTCSR
-
-
Highest priority
Lowest priority yes no FFFCh-FFFDh yes
(1) yes no no yes no yes no no
(4)
(4)
FFFEh-FFFFh
FFFAh-FFFBh
FFF8h-FFF9h
FFF6h-FFF7h
FFF4h-FFF5h
FFF2h-FFF3h yes FFF0h-FFF1h no
(3)
FFEEh-FFEFh no FFECh-FFEDh
FFEAh-FFEBh
FFE8h-FFE9h
FFE6h-FFE7h
FFE4h-FFE5h
FFE2h-FFE3h
FFE0h-FFE1h
1. This interrupt exits the MCU from “Auto Wake-up from Halt” mode only.
2. Whatever the sensitivity configuration, this interrupt cannot exit the MCU from Halt, Active-Halt and
AWUFH modes when a falling edge occurs.
3. This interrupt exits the MCU from “Wait” and “Active-Halt” modes only. Moreover IS4[1:0] =01 is the only safe configuration to avoid spurious interrupt in Halt and AWUFH modes.
4. These interrupts exit the MCU from “Active-Halt” mode only.
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