ST7LITEU05 ST7LITEU09 Central processing unit
15 PCH
7
Figure 11. CPU registers
0
ACCUMULATOR
RESET VALUE = XXh
7 0
X INDEX REGISTER
RESET VALUE = XXh
7 0
Y INDEX REGISTER
8
RESET VALUE = XXh
7 PCL 0
PROGRAM COUNTER
RESET VALUE = RESET VECTOR @ FFFEh-FFFFh
7
1
RESET VALUE = 1
1 1 H I N Z
1 1 X 1 X X
0
C
X
15 8 7 0
CONDITION CODE REGISTER
STACK POINTER
RESET VALUE = STACK HIGHER ADDRESS
1.
X = undefined value
The 8-bit condition code register contains the interrupt mask and four flags representative of the result of the instruction just executed. This register can also be handled by the PUSH and POP instructions.
Reset value: 111x 1xxx
7
1 1 1 N Z
0
C H
Read/write
I
These bits can be individually tested and/or controlled by specific instructions.
Bit 4 = H Half carry bit
This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU during an ADD or ADC instruction. It is reset by hardware during the same instructions.
0: No half carry has occurred.
Obsolete Product(s) - Obsolete Product(s)
This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutines.
Bit 3 = I Interrupt mask bit
This bit is set by hardware when entering in interrupt or by software to disable all interrupts except the TRAP software interrupt. This bit is cleared by software.
0: Interrupts are enabled.
1: Interrupts are disabled.
This bit is controlled by the RIM, SIM and IRET instructions and is tested by the JRM and JRNM instructions.
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