ST7LITEU05 ST7LITEU09 On-chip peripherals
Lite timer control/status register (LTCSR)
Reset Value: 0000 0x00 (0xh)
7
ICIE ICF TB TBIE TBF
Read / Write
WDGR WDGE
0
WDGD
Note:
Bit 7 = ICIE Interrupt Enable.
This bit is set and cleared by software.
0: Input Capture (IC) interrupt disabled
1: Input Capture (IC) interrupt enabled
Bit 6 = ICF Input Capture Flag.
This bit is set by hardware and cleared by software by reading the LTICR register.
Writing to this bit does not change the bit value.
0: No input capture
1: An input capture has occurred
After an MCU reset, software must initialise the ICF bit by reading the LTICR register
Bit 5 = TB Timebase period selection.
This bit is set and cleared by software.
0: Timebase period = t
OSC
* 8000 (1 ms @ 8 MHz)
1: Timebase period = t
OSC
* 16000 (2 ms @ 8 MHz)
Bit 4 = TBIE Timebase Interrupt enable .
This bit is set and cleared by software.
0: Timebase (TB) interrupt disabled
1: Timebase (TB) interrupt enabled
Bit 3 = TBF Timebase Interrupt Flag .
This bit is set by hardware and cleared by software reading the LTCSR register. Writing to this bit has no effect.
0: No counter overflow
1: A counter overflow has occurred
Bit 2 = WDGRF Force Reset/ Reset Status Flag
Obsolete Product(s) - Obsolete Product(s) hardware when a watchdog reset occurs and cleared by hardware or by software. It is cleared by hardware only when an LVD reset occurs. It can be cleared by software after a read access to the LTCSR register.
0: No watchdog reset occurred.
1: Force a watchdog reset (write), or, a watchdog reset occurred (read).
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On-chip peripherals ST7LITEU05 ST7LITEU09
Bit 1 = WDGE Watchdog Enable
This bit is set and cleared by software.
0: Watchdog disabled
1: Watchdog enabled
Bit 0 = WDGD Watchdog Reset Delay
This bit is set by software. It is cleared by hardware at the end of each t
WDG
period.
0: Watchdog reset not delayed
1: Watchdog reset delayed
Lite Timer Input Capture register (LTICR)
Reset value: 0000 0000 (00h)
7
ICR7 ICR6 ICR5 ICR4 ICR3
Read only
ICR2 ICR1
0
ICR0
Bits 7:0 = ICR[7:0] Input capture value
These bits are read by software and cleared by hardware after a reset. If the ICF bit in the
LTCSR is cleared, the value of the 8-bit up-counter is captured when a rising or falling edge occurs on the LTIC pin.
Address
(Hex.)
0B
0C
Table 27. Lite timer register map and reset values
Register label 7 6 5 4 3 2
LTCSR
Reset value
LTICR
Reset value
ICIE
0
ICR7
0
ICF
0
ICR6
0
TB
0
ICR5
0
TBIE
0
ICR4
0
1 0
TBF
0
ICR3
0
WDGRF x
ICR2
0
WDGE
0
ICR1
0
WDGD
0
ICR0
0
Obsolete Product(s) - Obsolete Product(s)
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