Central processing unit ST7LITEU05 ST7LITEU09
Note: Interrupts requested while I is set are latched and can be processed when I is cleared. By default an interrupt routine is not interruptible because the I bit is set by hardware at the start of the routine and reset by the IRET instruction at the end of the routine. If the I bit is cleared by software in the interrupt routine, pending interrupts are serviced regardless of the priority level of the current interrupt routine.
Bit 2 = N Negative bit
This bit is set and cleared by hardware. It is representative of the result sign of the last arithmetic, logical or data manipulation. It is a copy of the 7 th
bit of the result.
0: The result of the last operation is positive or null.
1: The result of the last operation is negative (that is, the most significant bit is a logic
1).
This bit is accessed by the JRMI and JRPL instructions.
Bit 1 = Z Zero bit
This bit is set and cleared by hardware. This bit indicates that the result of the last arithmetic, logical or data manipulation is zero.
0: The result of the last operation is different from zero.
1: The result of the last operation is zero.
This bit is accessed by the JREQ and JRNE test instructions.
Bit 0 = C Carry/borrow bit
This bit is set and cleared by hardware and software. It indicates an overflow or an underflow has occurred during the last arithmetic operation.
0: No overflow or underflow has occurred.
1: An overflow or underflow has occurred.
This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions. It is also affected by the “bit test and branch”, shift and rotate instructions.
6.3.5 Stack pointer (SP)
Reset Value: 00 FFh
15
0 0 0 0 0 0 0
8
0
Read/write
7 0
1 1 SP5 SP4 SP3
Read/write
SP2 SP1 SP0
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The stack pointer is a 16-bit register which is always pointing to the next free location in the stack. It is then decremented after data has been pushed onto the stack and incremented
before data is popped from the stack (see Figure 12 ).
Since the stack is 64 bytes deep, the 10 most significant bits are forced by hardware.
Following an MCU Reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer contains its reset value (the SP5 to SP0 bits are set) which is the stack higher address.
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Note:
Central processing unit
The least significant byte of the Stack Pointer (called S) can be directly accessed by a LD instruction.
When the lower limit is exceeded, the Stack Pointer wraps around to the stack upper limit, without indicating the stack overflow. The previously stored information is then overwritten and therefore lost. The stack also wraps in case of an underflow.
The stack is used to save the return address during a subroutine call and the CPU context during an interrupt. The user may also directly manipulate the stack by means of the PUSH and POP instructions. In the case of an interrupt, the PCL is stored at the first location pointed to by the SP. Then the other registers are stored in the next locations as shown in
Figure 12
.
• When an interrupt is received, the SP is decremented and the context is pushed on the stack.
• On return from interrupt, the SP is incremented and the context is popped from the stack.
A subroutine call occupies two locations and an interrupt five locations in the stack area.
CALL
Subroutine
@ 00C0h
Figure 12. Stack manipulation example
Interrupt event
PUSH Y POP Y IRET RET or RSP
SP
@ 00FFh
PCH
PCL
SP
CC
A
X
PCH
PCL
PCH
PCL
SP
Y
CC
A
X
PCH
PCL
PCH
PCL
SP
CC
A
X
PCH
PCL
PCH
PCL
SP
PCH
PCL
SP
1.
Stack higher address = 00FFh
Stack lower address = 00C0h
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