Compilation
Compilation
Before you can simulate a Verilog design, you must first create a library and compile the Verilog source code into that library. This section provides detailed information on compiling Verilog designs. For information on creating a design
library, see Chapter 2 - Design Libraries.
ModelSim Verilog compiles Verilog source code into retargetable, executable code, meaning that the library format is compatible across all supported platforms and that you can simulate your design on any platform without having to recompile your design specifically for that platform. As you compile your design, the resulting object code for modules and UDPs is generated into a library. By default, the compiler places results into the work library. You may specify an alternate library with the -work option. The following is a simple example of how to create a work library, compile a design, and simulate it:
Contents of top.v: module top; initial $display("Hello world"); endmodule
Create the work library:
% vlib work
Compile the design:
% vlog top.v
-- Compiling module top
Top level modules: top
View the contents of the work library (optional):
% vdir
MODULE top
Simulate the design:
% vsim -c top
# Loading work.top
VSIM 1> run -all
# Hello world
VSIM 2> quit
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Compilation
In this example, the simulator was run without the graphic interface by specifying the -c option. After the design was loaded, the simulator command run -all was entered, meaning to simulate until there are no more simulator events. Finally, the quit command was entered to exit the simulator. By default, a log of the simulation is written to the file "transcript" in the current directory.
Incremental compilation
By default, ModelSim Verilog supports incremental compilation of designs, thus saving compilation time when you modify your design. Unlike other Verilog simulators, there is no requirement that you compile the entire design in one invocation of the compiler (although, you may do so if desired).
You are not required to compile your design in any particular order because all module and UDP instantiations and external hierarchical references are resolved when the design is loaded by the simulator. Incremental compilation is made possible by deferring these bindings, and as a result some errors cannot be detected during compilation. Commonly, these errors include: modules that were referenced but not compiled, incorrect port connections, and incorrect hierarchical references.
The following example shows how a hierarchical design can be compiled in top down order:
Contents of top.v: module top; or2(n1, a, b); and2(n2, n1, c); endmodule
Contents of and2.v: module and2(y, a, b); output y; input a, b; and(y, a, b); endmodule
Contents of or2.v: module or2(y, a, b); output y; input a, b; or(y, a, b); endmodule
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Compile the design in top down order (assumes work library already exists):
% vlog top.v
-- Compiling module top
Top level modules: top
% vlog and2.v
-- Compiling module and2
Top level modules: and2
% vlog or2.v
-- Compiling module or2
Top level modules: or2
Note that the compiler lists each module as a top level module, although, ultimately, only "top" is a top level module. If a module is not referenced by another module compiled in the same invocation of the compiler, then it is listed as a top level module. This is just an informative message and can be ignored during incremental compilation. The message is more useful when you compile an entire design in one invocation of the compiler and need to know the top level module names for the simulator. For example,
% vlog top.v and2.v or2.v
-- Compiling module top
-- Compiling module and2
-- Compiling module or2
Top level modules: top
The most efficient method of incremental compilation is to manually compile only the modules that have changed. This is not always convenient, especially if your source files have compiler directive interdependencies (such as macros). In this case, you may prefer to always compile your entire design in one invocation of the compiler. If you specify the -incr option, the compiler will automatically determine which modules have changed and generate code only for those modules. This is not as efficient as manual incremental compilation because the compiler must scan all of the source code to determine which modules must be compiled.
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Compilation
The following is an example of how to compile a design with automatic incremental compilation:
% vlog -incr top.v and2.v or2.v
-- Compiling module top
-- Compiling module and2
-- Compiling module or2
Top level modules: top
Now, suppose that you modify the functionality of the "or2" module:
% vlog -incr top.v and2.v or2.v
-- Skipping module top
-- Skipping module and2
-- Compiling module or2
Top level modules: top
The compiler informs you that it skipped the modules "top" and "and2", and compiled "or2".
Automatic incremental compilation is intelligent about when to compile a module.
For example, adding a comment to your source code does not result in a recompile; however, changing the compiler command line options results in a recompile of all modules.
Library usage
All modules and UDPs in a Verilog design must be compiled into one or more libraries. One library is usually sufficient for a simple design, but you may want to organize your modules into various libraries for a complex design. If your design uses different modules having the same name, then you are required to put those modules in different libraries because design unit names must be unique within a library.
The following is an example of how you may organize your ASIC cells into one library and the rest of your design into another:
% vlib work
% vlib asiclib
% vlog -work asiclib and2.v or2.v
-- Compiling module and2
-- Compiling module or2
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Top level modules: and2 or2
% vlog top.v
-- Compiling module top
Top level modules: top
Note that the first compilation uses the -work asiclib option to instruct the compiler to place the results in the asiclib library rather than the default work library.
Since instantiation bindings are not determined at compile time, you must instruct the simulator to search your libraries when loading the design. The top level modules are loaded from the library named work unless you specify an alternate library with the -lib option. All other Verilog instantiations are resolved in the following order:
• Search libraries specified with -Lf options in the order they appear on the command line.
• Search the library specified in
"Verilog-XL `uselib compiler directive"
(5-72)
.
• Search libraries specified with -L options in the order they appear on the command line.
• Search the work library.
• Search the library explicitly named in the special escaped identifier instance name.
It is important to recognize that the work library is not necessarily a library named
work - the work library refers to the library containing the module that instantiates the module or UDP that is currently being searched for. This definition is useful if you have hierarchical modules organized into separate libraries and if sub-module names overlap among the libraries. In this situation you want the modules to search for their sub-modules in the work library first. This is accomplished by specifying -L work first in the list of search libraries.
For example, assume you have a top level module "top" that instantiates module
"modA" from library "libA" and module "modB" from library "libB".
Furthermore, "modA" and "modB" both instantiate modules named "cellA", but the definition of "cellA" compiled into "libA" is different from that compiled into
"libB". In this case, it is insufficient to just specify "-L libA - LlibB" as the search libraries because instantiations of "cellA" from "modB" resolve to the "libA" version of "cellA". The appropriate search library options are "-L work -L libA
-L libB".
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Compilation
Verilog-XL compatible compiler options
See
vlog
(CR-199)
for a complete list of compiler options. The options described here are equivalent to Verilog-XL options. Many of these are provided to ease the porting of a design to ModelSim Verilog.
+define+<macro_name>[=<macro_text>]
This option allows you to define a macro from the command line that is equivalent to the following compiler directive:
‘define <macro_name> <macro_text>
Multiple +define options are allowed on the command line. A command line macro overrides a macro of the same name defined with the ‘define compiler directive.
+incdir+<directory>
This option specifies directories to search for files included with ‘include compiler directives. By default, the current directory is searched first and then the directories specified by the +incdir options in the order they appear on the command line. You may specify multiple +incdir options as well as multiple directories separated by "+" in a single +incdir option.
+delay_mode_distributed
This option disables path delays in favor of distributed delays. See Delay modes
(5-81)
for details.
+delay_mode_path
This option sets distributed delays to zero in favor of path delays. See
Delay modes
(5-81)
for details.
+delay_mode_unit
This option sets path delays to zero and non-zero distributed delays to one time unit. See
Delay modes
(5-81)
for details.
+delay_mode_zero
This option sets path delays and distributed delays to zero. See
Delay modes
(5-81)
for details.
-f <filename>
This option reads more command line arguments from the specified text file.
Nesting of -f options is allowed.
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+mindelays
This option selects minimum delays from the "min:typ:max" expressions. If preferred, you may defer delay selection until simulation time by specifying the same option on the simulator.
+typdelays
This option selects typical delays from the "min:typ:max" expressions. If preferred, you may defer delay selection until simulation time by specifying the same option on the simulator.
+maxdelays
This option selects maximum delays from the "min:typ:max" expressions. If preferred, you may defer delay selection until simulation time by specifying the same option on the simulator.
-u
This option treats all identifiers in the source code as all uppercase.
The following options support source libraries in the same manner as Verilog-XL.
Note that these libraries are source libraries and are very different from the libraries that the ModelSim compiler uses to store compilation results. You may find it convenient to use these options if you are porting a design to ModelSim or if you are familiar with these options and prefer to use them.
Source libraries are searched after the source files on the command line are compiled.
If there are any unresolved references to modules or UDPs, then the compiler searches the source libraries to satisfy them. The modules compiled from source libraries may in turn have additional unresolved references that cause the source libraries to be searched again. This process is repeated until all references are resolved or until no new unresolved references are found. Source libraries are searched in the order they appear on the command line.
-v <filename>
This option specifies a source library file containing module and UDP definitions.
Modules and UDPs within the file are compiled only if they match previously unresolved references. Multiple -v options are allowed.
-y <directory>
This option specifies a source library directory containing module and UDP definitions. Files within this directory are compiled only if the file names match the names of previously unresolved references. Multiple -y options are allowed.
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+libext+<suffix>
This option works in conjunction with the -y option. It specifies file extensions for the files in a source library directory. By default the compiler searches for files without extensions. If you specify the +libext option, then the compiler will search for a file with the suffix appended to an unresolved name. You may specify only one +libext option, but it may contain multiple suffixes separated by "+". The extensions are tried in the order they appear in the +libext option.
+librescan
This option changes how unresolved references are handled that are added while compiling a module or UDP from a source library. By default, the compiler attempts to resolve these references as it continues searching the source libraries.
If you specify the +librescan option, then the new unresolved references are deferred until after the current pass through the source libraries. They are then resolved by searching the source libraries from the beginning in the order they are specified on the command line.
+nolibcell
By default, all modules compiled from a source library are treated as though they contain a ‘celldefine compiler directive. This option disables this default. The
‘celldefine directive only affects the PLI Access routines acc_next_cell and
acc_next_cell_load.
The -R option is not a Verilog-XL option, but it is used by ModelSim Verilog to combine the compile and simulate phases together as you may be used to with Verilog-
XL. It is not recommended that you regularly use this option because you will incur the unnecessary overhead of compiling your design for each simulation run. Mainly, it is provided to ease the transition to ModelSim Verilog.
-R <simargs>
This option instructs the compiler to invoke the simulator after compiling the design. The compiler automatically determines which top level modules are to be simulated. The command line arguments following -R are passed to the simulator, not the compiler. Place the -R option at the end of the command line or terminate the simulator command line arguments with a single "-" character to differentiate them from compiler command line arguments.
Verilog-XL ‘ uselib compiler directive
The ‘uselib compiler directive is an alternative source library management scheme to the -v, -y, and +libext compiler options. It has the advantage that a design may reference different modules having the same name. The ‘uselib compiler directive is not defined in the IEEE Std 1364-1995, but ModelSim supports it for compatability with Verilog-XL.
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The syntax for the ‘uselib directive is:
‘uselib <library_reference>...
where <library_reference> is: dir=<library_directory> | file=<library_file> | libext=<file_extension> | lib=<library_name>
In Verilog-XL, the library references are equivalent to command line options as follows: dir=<library_directory> file=<library_file> libext=<file_extension>
-y <library_directory>
-v <library_file>
+libext+<file_extension>
For example, the following directive
‘uselib dir=/h/vendorA libext=.v
is equivalant to the following command line options:
-y /h/vendorA +libext+.v
Since the ‘uselib directives are embedded in the Verilog source code, there is more flexibility in defining the source libraries for the instantiations in the design.
The appearance of a ‘uselib directive in the source code explicitly defines how instantiations that follow it are resolved, completely overriding any previous
‘uselib directives.
For example, the following code fragment shows how two different modules that have the same name can be instantiated within the same design:
‘uselib dir=/h/vendorA file=.v
NAND2 u1(n1, n2, n3);
‘uselib dir=/h/vendorB file=.v
NAND2 u2(n4, n5, n6);
This allows the NAND2 module to have different definitions in the vendorA and vendorB libraries.
ModelSim Verilog supports the ‘uselib directive in a different manner than
Verilog-XL. The library files referenced by the ‘uselib directive are not automatically compiled by ModelSim Verilog. The reason for this is that an object library is not allowed to contain multiple modules having the same name, and the results of a single invocation of the compiler can be placed in only one object library. Because it is an important feature of ‘uselib to allow a design to reference multiple modules having the same name, independent compilation of the source libraries referenced by the ‘uselib directives is required. Each source library
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