Below you will find brief information for software Elite EE/SE, software Special EE/SE. This manual provides information on how to use the ModelSim Elite and Special Editions for VHDL, Verilog, and Mixed-HDL simulation. The manual covers topics such as design libraries, projects, compilation, simulation, and mixed VHDL and Verilog designs.
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Supports VHDL, Verilog, and Mixed-HDL simulation
Provides a graphic interface for design entry and simulation
Includes a powerful Tcl scripting language for automating tasks
Supports Standard Delay Format (SDF) timing annotation
Offers a Foreign Language Interface (FLI) for integrating with other tools
Includes a Value Change Dump (VCD) file format for capturing simulation results
Provides support for Logic Modeling SmartModels and Hardware Models
Features a Performance Analyzer for profiling simulation performance
Includes Code Coverage analysis capabilities
Allows multiple logfiles, datasets, and virtual objects
A project is a collection of design files, libraries, and simulation settings that are used to simulate a design. Projects simplify the process of creating and managing simulations.
You can compile a VHDL design using the vcom command. The vcom command takes the design file as input and creates a library file containing the compiled design units.
SDF timing annotation is used to provide timing information for the design, which is used by the simulator to accurately model the timing behavior of the design.
The FLI allows you to interact with the simulator from a foreign language program. This allows you to create custom test benches, debug designs, or extend the simulator's capabilities.
What is the definition of VITAL?
VITAL stands for "VHDL Initiative Towards ASIC Libraries." It is the IEEE 1076.4 VITAL ASIC Modeling Specification. The simulator is compliant with this specification and includes accelerated VITAL packages (like VITAL v3.0) with optimized procedures built into the simulator kernel for improved performance.
