Cell Libraries has occured. The "on event" style is the default for propagating pulse errors (see
+pulse_e_style_onevent
(5-80)
).
+pulse_e_style_onevent
This option selects the "on event" style of propagating pulse errors (see +pulse_e
(5-79)
). A pulse error propagates to the output as an X, and the "on event" style is to schedule the X to occur at the same time and for the same duration that the pulse would have occured if it had propagated through normally. The "on event" style is the default for propagating pulse errors.
+sdf_nocheck_celltype
By default, the SDF annotator checks that the CELLTYPE name in the SDF file matches the module or primitive name for the CELL instance. It is an error if the names do not match. The +sdf_nocheck_celltype option disables this error check.
+sdf_verbose
This option displays a summary of the design objects annotated for each SDF file.
+transport_path_delays
By default, path delays operate in inertial mode (pulses smaller than the delay are filtered). The +transport_path_delays option selects transport mode for path delays. In transport mode, narrow pulses are propagated through path delays. Note that this option affects path delays only, and not primitives. Primitives always operate in inertial delay mode.
+typdelays
This option selects the typical value in min:typ:max expressions. The default is the typical value. This option has no effect if the min:typ:max selection was determined at compile time.
Cell Libraries
Model Technology is the first Verilog simulation vendor to pass the ASIC
Council’s Verilog test suite and achieve the "Library Tested and Approved" designation from Si2 Labs. This test suite is designed to ensure Verilog timing accuracy and functionality and is the first significant hurdle to complete on the way to achieving full ASIC vendor support. As a consequence, many ASIC and
FPGA vendors’ Verilog cell libraries are compatible with ModelSim Verilog.
The cell models generally contain Verilog "specify blocks" that describe the path delays and timing constraints for the cells. See section 13 in the IEEE Std 1364-
1995 for details on specify blocks, and section 14.5 for details on timing constraints. ModelSim Verilog fully implements specify blocks and timing
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Verilog Simulation ModelSim EE/SE User’s Manual
Cell Libraries constraints as defined in the IEEE Std 1364-1995 along with some Verilog-XL compatible extensions.
SDF timing annotation
ModelSim Verilog supports timing annotation from Standard Delay Format (SDF)
files. See Chapter 11 - Standard Delay Format (SDF) Timing Annotation for
details.
Delay modes
Verilog models may contain both distributed delays and path delays. The delays on primitives, UDPs, and continuous assignments are the distributed delays, whereas the port-to-port delays specified in specify blocks are the path delays.
These delays interact to determine the actual delay observed. Most Verilog cells use path delays exclusively, with the distributed delays set to zero. For example, module and2(y, a, b); input a, b; output y; and(y, a, b); specify
(a => y) = 5;
(b => y) = 5; endspecify endmodule
In the above two-input "and" gate cell, the distributed delay for the "and" primitive is zero, and the actual delays observed on the module ports are taken from the path delays. This is typical for most cells, but a complex cell may require non-zero distributed delays to work properly. Even so, these delays are usually small enough that the path delays take priority over the distributed delays. The rule is that if a module contains both path delays and distrubited delays, then the larger of the two delays for each path shall be used (as defined by the IEEE Std 1364-
1995). This is the default behavior, but you can specify alternate delay modes with compiler directives and options. These options and directives are compatible with
Verilog-XL. Compiler delay mode options take precedent over delay mode directives in the source code.
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