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کمپیوٹرز اور الیکٹرانکس سافٹ ویئر Model Technology Special EE/SE صارف دستی

Code Coverage commands. Model Technology Special EE/SE, Elite EE/SE

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Code Coverage commands

Code Coverage commands

The commands below are available once Code Coverage is active. Enable code coverage with the -coverage option to the

vsim

command

(CR-208)

.

The table below provides a brief description of the profile commands, follow the links for complete commmand syntax.

See the ModelSim EE/SE Command Reference for complete command details.

Command coverage clear

command

(CR-59)

coverage reload

command

(CR-60)

coverage report

command

(CR-61)

Description

used to clear all coverage data obtained during previous run commands used to seed the coverage statistics with the output of a previous coverage report command used to produce a textual output of the coverage statistics that have been gathered up to this point

8-138

ModelSim SE Code Coverage ModelSim EE/SE User’s Manual

/

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Съдържание

Software License Agreement

Model Technology Software License

Important Notice

Limited Warranty

ModelSim software versions documented in this manual

Standards supported

Sections in this document

Command reference

Text conventions

What is an "HDL item"

Where to find our documentation

Download a free PDF reader with Search

Online References - www.model.com

Design library contents

Design unit information

Design library types

Library management commands

Working with design libraries

Creating a library

Viewing and deleting library contents

Assigning a logical name to a design library

Moving a library

Specifying the resource libraries

VHDL resource libraries

Predefined libraries

Alternate IEEE libraries supplied

Rebuilding supplied libraries

Regenerating your design libraries

Verilog resource libraries

What is a project?

A new file extension

INI and MPF file comparison

The [Project] section in the .mpf file

Project operations

Creating a Project

Working with a Project

Compile a project

Simulating a project

Modifying a project

The project command

Compiling VHDL designs

Creating a design library

Invoking the VHDL compiler

Dependency checking

Simulating VHDL designs

Invoking the simulator from the Main window

Invoking Code Coverage with vsim

Using the TextIO package

Syntax for file declaration

Using STD_INPUT and STD_OUTPUT within ModelSim

TextIO implementation issues

Writing strings and aggregates

Reading and writing hexadecimal numbers

Dangling pointers

The ENDLINE function

The ENDFILE function

Using alternative input/output files

Providing stimulus

Obtaining the VITAL specification and source code

ModelSim VITAL compliance

VITAL compliance checking

Compiling and Simulating with accelerated VITAL packages

ModelSim variables

Incremental compilation

Verilog-XL compatible compiler options

Verilog-XL `uselib compiler directive

Invoking the simulator

Simulation resolution limit

Event order issues

Verilog-XL compatible simulator options

SDF timing annotation

IEEE Std 1364-1995 system tasks

Verilog-XL compatible system tasks

Compiler Directives

IEEE Std 1364-1995 compiler directives

Verilog-XL compatible compiler directives

Using the Verilog PLI

Registering PLI applications

Compiling and linking PLI applications

The callback reason argument

The sizetf callback function

Third party PLI applications

Support for VHDL objects

IEEE Std 1364 ACC routines

IEEE Std 1364 TF routines

Verilog-XL compatible routines

Separate compilers, common libraries

Mapping data types

Verilog parameters

VHDL and Verilog ports

VHDL instantiation of Verilog design units

Verilog instantiation criteria

Component declaration

vgencomp component declaration

Verilog instantiation of VHDL design units

VHDL instantiation criteria

Introducing Performance Analysis

A Statistical Sampling Profiler

Getting Started

Interpreting the data

Viewing Performance Analyzer Results

Interpreting the Name Field

Interpreting the %Under and %In Fields

Differences in the Ranked and Hierarchical Views

Ranked/Hierarchical Window Features

The report option

Setting preferences with Tcl variables

Performance Analyzer commands

Enabling Code Coverage

The coverage_summary window

Coverage Summary window preferences

Code Coverage commands

Multiple logfiles and datasets

Opening and viewing datasets

Using datasets with ModelSim commands

Restricting the dataset prefix display

Virtual Objects (User-defined buses, and more)

Virtual signals

Virtual functions

Virtual regions

Logfile and virtual commands reference table

Window overview

Window features

Quick access toolbars

Command history

Automatic window updating

Finding names, searching for values, and locating cursors

Sorting HDL items

Multiple window copies

Customizing menus and buttons

Combine signals into a user-defined bus

Tree window hierarchical view

The Main window menu bar

The Main window tool bar

The Main window status bar

Editing the command line, the current source file, and notepads

Dataflow window

The Dataflow window menu bar

Tracing HDL items with the Dataflow window

Saving the Dataflow window as a Postscript file

HDL items you can view

The List window menu bar

Setting List window display properties

Adding HDL items to the List window

Editing and formatting HDL items in the List window

Examining simulation results with the List window

Finding items by name in the List window

Searching for item values in the List window

Setting time markers in the List window

List window keyboard shortcuts

Saving List window data to a file

The Process window menu bar

The Signals window menu bar

Selecting HDL item types to view

Forcing signal and net values

Adding HDL items to the Wave and List windows or a logfile

Finding HDL items in the Signals window

Defining clock signals

The Source window menu bar

The Source window tool bar

Editing the source file in the Source window

Checking HDL item values and descriptions

Setting Source window options

Structure window

The Structure window menu bar

Variables window

The Variables window menu bar

Wave window panes

HDL items you can view

The Wave window menu bar

Wave window tool bar

Adding HDL items in the Wave window

Combining and grouping items in the Wave window

Editing and formatting HDL items in the Wave window

Setting Wave window display properties

Sorting a group of HDL items

Finding items by name or value in the Wave window

Searching for item values in the Wave window

Using time cursors in the Wave window

Zooming - changing the waveform display range

Wave window keyboard shortcuts

Printing and saving waveforms

Compiling with the graphic interface

Locating source errors during compilation

Setting default compile options

Simulating with the graphic interface

Design selection page

VHDL settings page

Verilog settings page

SDF settings page

Setting default simulation options

The Button Adder

The Macro Helper

The Tcl Debugger

The GUI Expression Builder

The FPGA Library Manager

Graphic interface commands

Customizing the interface

Specifying SDF files for simulation

Instance specification

SDF specification with the GUI

Errors and warnings

SDF to VHDL generic matching

Resolving errors

The $sdf_annotate system task

SDF to Verilog construct matching

Optional edge specifications

Optional conditions

Rounded timing values

SDF for Mixed VHDL and Verilog Designs

Interconnect delays

Troubleshooting

Specifying the wrong instance

Mistaking a component or module name for an instance label

Forgetting to specify the instance

Obtaining the SDF specification

Using the VHDL FLI

Using the VHDL FLI with foreign architectures

Using the VHDL FLI with foreign subprograms

Using checkpoint/restore with the FLI

Support for Verilog instances

Support for Windows platforms

FLI function descriptions

Mapping to VHDL data types

VHDL FLI examples

Compiling and linking FLI applications

Windows NT/95/98 platforms

Solaris platform

SunOS 4 platform

IBM RISC/6000 platform

The purpose of tracing files

Invoking a trace

ModelSim VCD commands and VCD tasks

Resimulating a VHDL design from a VCD file

Extracting the proper stimulus for bidirectional ports

Specifying a filename and state mappings

Creating the VCD file

A VCD file from source to output

VHDL source code

VCD simulator commands

Capturing port driver data with -dumpports

Supported TSSI states

Strength values

Port identifier code

Example VCD output from -dumpports

VHDL SmartModel interface

Creating foreign architectures with sm_entity

Command channel

SmartModel Windows

Verilog SmartModel interface

LMTV usage documentation

Linking the LMTV interface to the simulator

Compiling Verilog shells

VHDL Hardware Model interface

Creating foreign architectures with hm_entity

Hardware model commands

Tcl features within ModelSim

Tcl print references

Tcl online references

Tcl command syntax

if command syntax

set command syntax

Command substitution

Command separator

Multiple-line commands

Evaluation order

Tcl relational expression evaluation

Variable substitution

System commands

List processing

VSIM Tcl commands

ModelSim Tcl time commands

Tcl examples - UNIX only

ModelSim worldwide contacts

Technical support - by telephone

Mentor Graphics customers In North America

Mentor Graphics customers outside North America

Model Technology customers worldwide

Technical support - electronic support services

Mentor Graphics customers

Model Technology customers

Technical support - other channels

Mentor customers: getting the latest version via FTP

Model Technology customers: getting the latest version via FTP

FLEXlm Licenses

Where to obtain your license

If you have trouble with licensing

All customers: ModelSim licensing

All customers: maintenance renewals and licenses

All customers: license transfers and server changes

Additional licensing details

Variable settings report

Personal preferences

Returning to the original ModelSim defaults

Environment variables

ModelSim Environment Variables

Setting environment variables in Windows

Referencing environment variables within ModelSim

Removing temp files (VSOUT)

Preference variables located in INI and MPF files

[Library] library path variables

[vcom] VHDL compiler control variables

[vlog] Verilog compiler control variables

[vsim] simulator control variables

[lmc] Logic Modeling variables

[Project] project file section (MPF files only)

Setting variables in INI / MPF files

Reading variable values from the INI file

Variable functions

More preferences

Preference variables located in TCL files

User-defined variables

Viewing the default preference file (pref.tcl)

Preference variable arrays

Main window preference variables

The Main window uses preference variables similar to other ModelSim window to conrol colors and f...

Individual preference variables

The addons variable

Setting Tcl preference variables

More preferences

Preference variable loading order

Simulator state variables

Referencing simulator state variables

Wave window keyboard shortcuts

List window keyboard shortcuts

Command shortcuts

Command history shortcuts

Editing the command line, the current source file, and notepads

Right mouse button

Starting the license server daemon

Locating the license file

Controlling the license file search

Automatic start at boot time

What to do if another application uses FLEXlm

Format of the license file

Format of the daemon options file

License administration tools

How to use checkpoint/restore

The difference between checkpoint/restore and restarting

Using macros with restart and checkpoint/restore

Running command-line and batch-mode simulations

Command-line mode

Passing parameters to macros

Source code security and -nodebug

Saving and viewing waveforms

Setting up libraries for group use

Bus contention checking

Bus float checking

Design stability checking

Toggle checking

Detecting infinite zero-delay loops

Referencing source files with location maps

Using location mapping

Pathname syntax

How location mapping works

Mapping with Tcl variables

Accelerate simulation by locking memory under HP-UX 10.2

Modeling memory in VHDL

Setting up a List trigger with Expression Builder

GUI changes and new features

Command and variable changes

Documentation changes

Find 5.2 features in the 5.3 interface

Main window toolbar buttons and menu selections

Main window menu changes

File menu selections

View menu selections

Library menu selections

Run menu selections

Options menu selections

Window menu selections

Help menu selections

List window menu changes

Prop menu selections

Process window menu changes

File menu selections

Signals window menu changes

Edit menu selections

Structure window menu changes

File menu selections

Edit menu selections

Variables window menu changes

Edit menu selections

Wave window menu changes

File menu selections

Edit menu selections

Prop menu selections

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