Troubleshooting
Troubleshooting
Several common mistakes in SDF annotation are outlined below.
Specifying the wrong instance
By far, the most common mistake in SDF annotation is to specify the wrong instance to the simulator’s SDF options. The most common case is to leave off the instance altogether, which is the same as selecting the top-level design unit. This is almost always wrong because the instance paths in the SDF are relative to the
ASIC or FPGA model, which is usually instantiated under a top-level testbench.
A common example for both VHDL and Verilog test benches is provided below.
For simplicity, the test benches do nothing more than instantiate a model that has no ports.
VHDL testbench entity testbench is end; architecture only of testbench is component myasic end component; begin end; dut : myasic;
Verilog testbench module testbench; myasic dut(); endmodule
The name of the model is myasic and the instance label is dut. For either testbench, an appropriate simulator invocation might be: vsim -sdfmax /testbench/dut=myasic.sdf testbench
Optionally, you may leave off the name of the top-level: vsim -sdfmax /dut=myasic.sdf testbench
The important point is to select the instance that the SDF is intended for. If the model is deep within the design hierarchy, an easy way to find the instance name is to first invoke the simulator without SDF options, open the structure window, navigate to the model instance, select it, and enter the
environment
command
(CR-80)
. This command displays the instance name that should be used in the SDF command-line option.
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Standard Delay Format (SDF) Timing Annotation ModelSim EE/SE User’s Manual
Troubleshooting
Mistaking a component or module name for an instance label
Another common error is to specify the component or module name rather than the instance label. For example, the following invocation is wrong for the above testbenches: vsim -sdfmax /testbench/myasic=myasic.sdf testbench
This results in the following error message:
ERROR: myasic.sdf:
The design does not have an instance named ’/testbench/myasic’.
Forgetting to specify the instance
If you leave off the instance altogether, then the simulator issues a message for each instance path in the SDF that is not found in the design. For example, vsim -sdfmax myasic.sdf testbench
Results in:
ERROR: myasic.sdf:
Failed to find INSTANCE ’/testbench/u1’
ERROR: myasic.sdf:
Failed to find INSTANCE ’/testbench/u2’
ERROR: myasic.sdf:
Failed to find INSTANCE ’/testbench/u3’
ERROR: myasic.sdf:
Failed to find INSTANCE ’/testbench/u4’
ERROR: myasic.sdf:
Failed to find INSTANCE ’/testbench/u5’
WARNING: myasic.sdf:
This file is probably applied to the wrong instance.
WARNING: myasic.sdf:
Ignoring subsequent missing instances from this file.
After annotation is done, the simulator issues a summary of how many instances were not found and possibly a suggestion for a qualifying instance:
WARNING: myasic.sdf:
Failed to find any of the 358 instances from this file.
WARNING: myasic.sdf:
Try instance ’/testbench/dut’ - it contains all instance paths from this file.
The simulator recommends an instance only if the file was applied to the top-level and a qualifying instance is found one level down.
Also see
"Resolving errors"
(11-285)
for specific VHDL VITAL SDF
troubleshooting.
ModelSim EE/SE User’s Manual Standard Delay Format (SDF) Timing Annotation
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