System Tasks. Model Technology Special EE/SE, Elite EE/SE

Below you will find brief information for software Elite EE/SE, software Special EE/SE. This manual provides information on how to use the ModelSim Elite and Special Editions for VHDL, Verilog, and Mixed-HDL simulation. The manual covers topics such as design libraries, projects, compilation, simulation, and mixed VHDL and Verilog designs.

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System Tasks

Distributed delay mode

In distributed delay mode the specify path delays are ignored in favor of the distributed delays. Select this delay mode with the +delay_mode_distributed compiler option or the ‘delay_mode_distributed compiler directive.

Path delay mode

In path delay mode the distributed delays are set to zero. Select this delay mode with the +delay_mode_path compiler option or the ‘delay_mode_path compiler directive.

Unit delay mode

In unit delay mode the distributed delays are set to one (the unit is the time_unit specified in the ‘timescale directive), and the specify path delays and timing constraints are ignored. Select this delay mode with the +delay_mode_unit compiler option or the ‘delay_mode_unit compiler directive.

Zero delay mode

In zero delay mode the distributed delays are set to zero, and the specify path delays and timing constraints are ignored. Select this delay mode with the

+delay_mode_zero compiler option or the ‘delay_mode_zero compiler directive.

System Tasks

The IEEE Std 1364-1995 defines many system tasks as part of the Verilog language, and ModelSim Verilog supports all of these along with several nonstandard Verilog-XL system tasks. The system tasks listed in this chapter are built into the simulator, although some designs depend on user-defined system tasks implemented with the Programming Language Interface (PLI). If the simulator issues warnings regarding undefined system tasks, then it is likely that these system tasks are defined by a PLI application that must be loaded by the simulator.

IEEE Std 1364-1995 system tasks

The following system tasks are described in detail in the IEEE Std 1364-1995.

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System Tasks

Timescale tasks

$printtimescale

$timeformat

Probabilistic distribution functions

$dist_chi_square

$dist_erlang

$dist_exponential

$dist_normal

$dist_poisson

$dist_t

$dist_uniform

Display tasks

$display

$displayb

$displayh

$displayo

$monitor

$monitorb

$monitorh

$monitoro

Simulator control tasks

$finish

$timeformat

Simulation time functions

$realtime

$stime

$time

Value change dump

(VCD) file tasks

$dumpall

$dumpfile

$dumpflush

$dumplimit

$dumpoff

$dumpon

$dumpvars

File I/O tasks

$fclose

$fdisplay

$fdisplayb

$fdisplayh

$fdisplayo

$fmonitor

$fmonitorb

$fmonitorh

Conversion functions for reals

$bitstoreal

$itor

$realtobits

$rtoi

PLA modeling tasks

$async$and$array

$async$nand$array

$async$or$array

$async$nor$array

$async$and$plane

$async$nand$plane

$async$or$plane

$async$nor$plane

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System Tasks

Display tasks

$monitoroff

$monitoron

$strobe

$strobeb

$strobeh

$strobeo

$write

$writeb

$writeh

$writeo

Timing check task

$hold

$nocharge

$period

$recovery

$setup

$setuphold

$skew

$width

File I/O tasks

$fmonitoro

$fopen

$fstrobe

$fstrobeb

$fstrobeh

$fstrobeo

$fwrite

$fwriteb

$fwriteh

$fwriteo

$readmemb

$readmemh

Stochastic analysis tasks

$q_add

$q_exam

$q_full

$q_initialize

$q_remove

$random

PLA modeling tasks

$sync$and$array

$sync$nand$array

$sync$or$array

$sync$nor$array

$sync$and$plane

$sync$nand$plane

$sync$or$plane

$sync$nor$plane

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System Tasks

Verilog-XL compatible system tasks

The following system tasks are provided for compatibility with Verilog-XL.

Although they are not part of the IEEE standard, they are described in an annex of the IEEE Std 1364-1995.

$countdrivers

$getpattern

$sreadmemb

$sreadmemh

The following system tasks are also provided for compatibility withVerilog-XL, but they are not described in the IEEE Std 1364-1995.

$sdf_annotate

See:

The $sdf_annotate system task

(11-286)

$system("operating system shell command");

This system task executes the specified operating system shell command and displays the result. For example, to list the contents of the working directory on Unix:

$system("ls");

$test$plusargs("plus argument")

This system function tests for the presence of a specific plus argument on the simulator’s command line. It returns 1 if the plus argument is present; otherwise, it returns 0. For example, to test for +verbose: if ($test$plusargs("verbose"))

$display("Executing cycle 1");

$removal(reference_event, data_event, limit, [notifier])

The $removal timing check issues a timing violation under the following condition:

0 < ((time of reference event) - (time of data event)) < limit

$recrem(reference_event, data_event, recovery_limit, removal_limit, [notifier],

[tstamp_cond], [tcheck_cond], {delayed-reference], [delayed_data])

The $recrem timing check is a combined $recovery and $removal timing check. It behaves very much like the $setuphold timing check, along with the extensions for negative constraints and an alternate method of conditioning

(see the description of $setuphold below)

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System Tasks

The following system tasks are extended to provide additional functionality for negative timing constraints and an alternate method of conditioning, as does

Verilog-XL.

$setuphold(clk_event, data_event, setup_limit, hold_limit, [notifier],

[tstamp_cond], [tcheck_cond], [delayed_clk], [delayed_data])

The tstamp_cond argument conditions the data_event for the setup check and the clk_event for the hold check. This alternate method of conditioning precludes specifying conditons in the clk_event and data_event arguments.

The tcheck_cond argument conditions the data_event for the hold check and the clk_event for the setup check. This alternate method of conditioning precludes specifying conditons in the clk_event and data_event arguments.

The delayed_clk argument is a net that is continuously assigned the value of the net specified in the clk_event. The delay is non-zero if the setup_limit is negative, zero otherwise.

The delayed_data argument is a net that is continuously assigned the value of the net specified in the data_event. The delay is non-zero if the hold_limit is negative, zero otherwise.

The delayed_clk and delayed_data arguments are provided to ease the modeling of devices that may have negative timing constraints. The model’s logic should reference the delayed_clk and delayed_data nets in place of the normal clk and data nets. This ensures that the correct data is latched in the presence of negative constraints. The simulator automatically calculates the delays for delayed_clk and delayed_data such that the correct data is latched as long as a timing constraint has not been violated.

$recovery(reference event, data_event, removal_limit, recovery_limit,

[notifier], [tstamp_cond], [tcheck_cond], [delayed_reference],

[delayed_data])

The $recovery system task normally takes a recovery_limit as the third argument and an optional notifier as the fourth argument. By specifying a limit for both the third and fourth arguments, the $recovery timing check is transformed into a combination removal and recovery timing check similar to the $recrem timing check. The only difference is that the removal_limit and recovery_limit are swapped.

The following system tasks are Verilog-XL system tasks that are not implemented in ModelSim Verilog, but have equivalent simulator commands.

$input("filename")

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Key features

Supports VHDL, Verilog, and Mixed-HDL simulation
Provides a graphic interface for design entry and simulation
Includes a powerful Tcl scripting language for automating tasks
Supports Standard Delay Format (SDF) timing annotation
Offers a Foreign Language Interface (FLI) for integrating with other tools
Includes a Value Change Dump (VCD) file format for capturing simulation results
Provides support for Logic Modeling SmartModels and Hardware Models
Features a Performance Analyzer for profiling simulation performance
Includes Code Coverage analysis capabilities
Allows multiple logfiles, datasets, and virtual objects

Frequently asked questions

A project is a collection of design files, libraries, and simulation settings that are used to simulate a design. Projects simplify the process of creating and managing simulations.

You can compile a VHDL design using the vcom command. The vcom command takes the design file as input and creates a library file containing the compiled design units.

SDF timing annotation is used to provide timing information for the design, which is used by the simulator to accurately model the timing behavior of the design.

The FLI allows you to interact with the simulator from a foreign language program. This allows you to create custom test benches, debug designs, or extend the simulator's capabilities.

User questions

Patricia I.

What is the definition of VITAL?

VITAL stands for "VHDL Initiative Towards ASIC Libraries." It is the IEEE 1076.4 VITAL ASIC Modeling Specification. The simulator is compliant with this specification and includes accelerated VITAL packages (like VITAL v3.0) with optimized procedures built into the simulator kernel for improved performance.