Wave window menu changes
Wave window menu changes
File menu selections
See
"The Wave window menu bar"
(10-217)
for complete menu option details.
5.2
5.3
5.2 Wave window
File menu new selections
5.3 Wave window
File menu
ModelSim EE/SE User’s Manual What’s new in ModelSim 5.3
F-481
Wave window menu changes
Edit menu selections
See
"The Wave window menu bar"
(10-217)
for complete menu option details.
5.2
5.3
5.2 Wave window
Edit menu
5.3 Wave window
Edit menu new selections
F-482
What’s new in ModelSim 5.3
ModelSim EE/SE User’s Manual
Wave window menu changes
Prop menu selections
The Prop menu selections in the 5.2 version have been moved to the Edit and
Format menus of the Wave window in the 5.3 version. See
"The Wave window menu bar"
(10-217)
for complete menu option details.
5.3
5.2
5.2 Wave window
Prop menu
ModelSim EE/SE User’s Manual
5.3 Wave window
Edit menu
5.3 Wave window
Format menu
What’s new in ModelSim 5.3
F-483
F-484
What’s new in ModelSim 5.3
ModelSim EE/SE User’s Manual
Index
A
architecture simulator state variable
420
argc simulator state variable
420
AssertFile .ini file variable
398
AssertionFormat .ini file variable
398
Assertions selecting severity that stops simulation
262
B
Batch mode
440
Break on assertion
262
BreakOnAssertion .ini file variable
398
Breakpoints deleting
200
setting
200
viewing
200
Button Adder (add buttons to windows)
265
C
C interface, see Foreign language interface
297
Cell libraries
80
Checkpoint/restore
438
CheckpointCompressMode .ini file variable
398
CheckSynthesis .ini file variable
396
Code Coverage
133
coverage clear command
134
coverage reload command
135
coverage report command
135
,
138
coverage_summary window
136
enabling code coverage
134
,
138
invoking code coverage with vsim
54
Tcl control variables
137
Colors
ModelSim EE/SE User’s Manual changing window colors with the GUI
414
Command reference
26
CommandHistory .ini file variable
398
Command-line mode
440
,
441
Commands graphic interface commands
277
library management commands
33
VSIM Tcl commands
378
Compilation and Simulation
Verilog
64
–
106
VHDL
51
–
61
Compiler directives
87
IEEE Std 1364-1995
88
XL compatible compiler directives
89
Compiling locating source errors
245
projects
49
Verilog
XL ’uselib compiler directive
72
XL compatible options
70
Verilog designs
65
incremental compilation
66
VHDL designs
52
Component declaration generating VHDL from Verilog
114
with vgencomp
114
ConcurrentFileLimit .ini file variable
398
configuration simulator state variable
420
Conventions text and command syntax
26
coverage clear command
134
coverage reload command
135
coverage report command
135
,
138
coverage_summary window
136
Cur_Top_DUs .mpf file variable
402
D
Dataflow window (see also, Windows)
170
Index -
485
Dataset Browser
141
Datasets restrict dataset prefix display
143
the Dataset Browser
141
DefaultForceKind .ini file variable
398
DefaultRadix .ini file variable
399
Delay specifying stimulus delay
196
DelayFileOpen .ini file variable
399
Delta collapse deltas in the List window
178
referencing simulator iteration as a simulator state variable
420
delta simulator state variable
420
Descriptions of HDL items
204
Design hierarchy viewing in Structure window
206
Design library assigning a logical name
37
creating
33
for VHDL design units
52
mapping search rules
39
resource type
32
working type
32
Design units
32
viewing hierarchy
155
Directories moving libraries
39
See also, Library
DOPATH environment variable
391
DOPATH simulator control variable
412
E
Editing in notepad windows
167
,
426
in the Main window
167
,
426
in the Source window
167
,
426
EDITOR environment variable
391
Email
Model Technology’s email address
30
486
- Index entity simulator state variable
420
Environment variables
391
expanding with FindProjectEntry FLI function
313
for locating license file
430
in PrefMain(file) variable
411
loading PLI files with PLIOBJS
96
location of modelsim.ini file
420
overriding with DOPATH simulator control variable
412
referencing from ModelSim command line
393
referencing with VHDL FILE variable
393
setting before compiling or simulating
391
setting in Windows
392
specify transcript file location with TranscriptFile
400
specifying library locations in modelsim.ini file
395
used in Solaris linking for FLI and PLI
94
,
332
using with location mapping
449
variable substitution using Tcl
376
within FOREIGN attribute string
298
Errors during compilation, locating
245
Explicit .ini file variable
396
Expression Builder, see GUI expression builder
F
Finding a cursor in the Wave window
234
a marker in the List window
187
Finding names, and searching for values in windows
154
FLEXlm lmdown license server utility
435
lmgrd license server utility
435
lmremove license server utility
435
lmreread license server utility
436
lmstat license server utility
434
FLEXlm license manager
429
–
436
FLI, see Foreign language interface
297
Fonts changing fonts with the GUI
415
Foreign language interface
ModelSim EE/SE User’s Manual
declaring FOREIGN attribute
298
enumeration object values
329
examples
330
function descriptions, see also mti_ functions
309
mapping to VHDL data types
328
restrictions on ports and generics
300
tracing
105
,
334
using checkpoint/restore with the FLI
305
using with foriegn architectures
298
using with foriegn subprograms
300
FPGA Library Manager
274
G
GenerateFormat .ini file variable
399
Generics
VHDL
108
Graphic interface
149
–
273
GUI_expression_format
GUI expression builder
272
H
Hazard .ini file variable (VCOM)
396
Hazard .ini file variable (VLOG)
397
Hierarchical profile
123
history shortcuts
425
HOME environment variable
391
Home page
Model Technology’s home-page URL
30
how_Warning5 .ini file variable
396
I
ieee .ini file variable
395
IgnoreError .ini file variable
399
IgnoreFailure .ini file variable
399
IgnoreNote .ini file variable
399
IgnoreVitalErrors .ini file variable
396
IgnoreWarning .ini file variable
399
Initialization file, see Project files
Installation locating the license file
430
Instantiation label
207
Iteration_limit detecting infinite zero-delay loops
448
IterationLimit .ini file variable
399
K
Keyboard shortcuts, List window
187
,
424
Keyboard shortcuts, Wave window
237
,
423
L
<Lib>_script .mpf file variable
402
Libraries alternate IEEE libraries
41
creating design libraries
33
deleting library contents
35
design units
32
FPGA Library Manager
274
ieee_numeric
41
ieee_synopsis
41
library management commands
33
mapping
37
mapping from the command line
38
mapping hierarchy
404
mapping search rules
39
moving
39
naming
37
predefined
40
rebuilding ieee_numeric
41
rebuilding ieee_synopsis
41
refreshing library images
41
resource libraries
32
setting up for groups
445
std
40
verilog
68
,
110
VHDL library clause
40
viewing library contents
35
ModelSim EE/SE User’s Manual Index -
487
work library
32
working libraries
32
library simulator state variable
420
License locating the license file
430
License .ini file variable
399
List window setting triggers
177
,
456
List window (see also, Windows)
174
LM_LICENSE_FILE environment variable
391
Locating source errors during compilation
245
Location maps referencing source files
449
LockedMemory .ini file variable
400
,
462
Logic Modeling
SmartModel command channel
354
compiling Verilog shells
357
SmartModel Windows
355
lmcwin commands
355
memory arrays
356
M
MacroNestingLevel simulator state variable
420
Macros (do files) depth of nesting, simulator state variable
420
parameter as a simulator state variable (n)
420
parameter total as a simulator state variable
420
passing parameters to
442
startup macros
404
Main window (see also, Windows)
158
Memory locked memory
451
modeling in VHDL
452
Menus customizing menus and buttons
155
Dataflow window
171
List window
175
Main window
159
Process window
190
488
- Index
Signals window
193
Source window
201
Structure window
207
tearing off or pinning menus
154
Variables window
210
Wave window
217
Messages turning off assertion messages
405
turning off warnings from arithmetic packages
405
MGC_LOCATION_MAP environment variable
391
MODEL_TECH environment variable
391
MODEL_TECH_FPGA environment variable
391
MODEL_TECH_TCL environment variable
391
Modeling memory in VHDL
452
ModelSim custom setup with daemon options
432
license file
430
MODELSIM environment variable
392
modelsim.ini, see Project files
MODELSIM_TCL environment variable
392
mti_AddCommand
309
mti_AddEnvCB
309
mti_AddInputReadyCB
309
mti_AddLoadDoneCB
309
mti_AddOutputReadyCB
309
mti_AddQuitCB
309
mti_AddRestartCB
310
mti_AddRestoreCB
310
mti_AddSaveCB
310
mti_AddSimStatusCB
310
mti_AddSocketInputReadyCB
310
mti_AddSocketOutputReadyCB
310
mti_AddTclCommand
310
mti_AskStdin
310
mti_Break
311
mti_Cmd
311
mti_Command
311
mti_CreateArrayType
311
mti_CreateDriver
311
mti_CreateEnumType
312
mti_CreateProcess
312
mti_CreateRealType
312
ModelSim EE/SE User’s Manual
mti_CreateRegion
312
mti_CreateScalarType
312
mti_CreateSignal
312
mti_Delta
312
mti_Desensitize
312
mti_ElementType
313
mti_FatalError
313
mti_FindDriver
313
mti_FindPort
313
mti_FindProjectEntry
313
mti_FindRegion
313
mti_FindSignal
313
mti_FindVar
314
mti_FirstLowerRegion
314
mti_FirstProcess
314
mti_FirstSignal
314
mti_FirstVar
314
mti_Free
314
mti_GetArrayElementType
315
mti_GetArraySignalValue
315
mti_GetArrayVarValue
315
mti_GetCallingRegion
315
mti_GetCheckpointFilename
315
mti_GetCurrentRegion
315
mti_GetDriverSubelements
315
mti_GetEnumValues
316
mti_GetGenericList
316
mti_GetLibraryName
316
mti_GetNextEventTime
316
mti_GetNextNextEventTime
316
mti_GetNumRecordElements
316
mti_GetPrimaryName
317
mti_GetProcessName
317
mti_GetProductVersion
317
mti_GetRegionFullName
317
mti_GetRegionKind
317
mti_GetRegionName
317
mti_GetRegionSourceName
317
mti_GetResolutionLimit
317
mti_GetSecondaryName
317
mti_GetSignalMode
318
mti_GetSignalName
318
ModelSim EE/SE User’s Manual mti_GetSignalNameIndirect
318
mti_GetSignalRegion
318
mti_GetSignalSubelements
318
mti_GetSignalType
319
mti_GetSignalValue
319
mti_GetSignalValueIndirect
319
mti_GetTopRegion
319
mti_GetTraceLevel
319
mti_GetTypeKind
319
mti_GetVarAddr
319
mti_GetVarImage
320
mti_GetVarImageById
320
mti_GetVarName
320
mti_GetVarSubelements
320
mti_GetVarType
321
mti_GetVarValue
321
mti_GetVarValueIndirect
321
mti_HigherRegion
321
mti_Image
321
mti_Interp
321
mti_IsColdRestore
322
mti_IsFirstInit
322
mti_IsPE
322
mti_IsRestore
322
mti_Malloc
322
mti_NextProcess
322
mti_NextRegion
322
mti_NextSignal
322
mti_NextVar
323
mti_Now
323
mti_NowIndirect
323
mti_NowUpper
323
mti_PrintMessage
323
mti_Quit
323
mti_Realloc
323
mti_RemoveEnvCB
323
mti_RemoveLoadDoneCB
323
mti_RemoveQuitCB
324
mti_RemoveRestartCB
324
mti_RemoveRestoreCB
324
mti_RemoveSaveCB
324
mti_RemoveSimStatusCB 324
Index -
489
mti_Resolution
324
mti_RestoreBlock
324
mti_RestoreChar
324
mti_RestoreLong
324
mti_RestoreProces
324
mti_RestoreShort
324
mti_RestoreString
325
mti_SaveBlock
325
mti_SaveChar
325
mti_SaveLong
325
mti_SaveShort
325
mti_SaveString
325
mti_ScheduleDriver
325
mti_ScheduleWakeup
325
mti_Sensitize
325
mti_SetDriverOwner
326
mti_SetSignalValue
326
mti_SetVarValue
326
mti_SignalImage
326
MTI_TF_LIMIT environment variable
391
mti_TickDir
326
mti_TickHigh
326
mti_TickLeft
327
mti_TickLength
327
mti_TickLow
327
mti_TickRight
327
mti_TraceActivate
327
mti_TraceOff
327
mti_TraceOn
327
mti_TraceSkipID
327
mti_TraceSuspend
327
mti_WriteProjectEntry
327
Multiple drivers on unresolved signal
248
N
n simulator state variable
420
Nets adding to the Wave and List windows
197
displaying in Dataflow window
170
displaying values in Signals window
192
490
- Index forcing signal and net values
195
saving values as binary log file
197
viewing waveforms
212
Next and previous edges, finding
237
,
423
No space in time literal
247
NoDebug .ini file variable (VCOM)
396
NoDebug .ini file variable (VLOG)
397
Notepad windows, text editing
167
,
426
NoVital .ini file variable
396
NoVitalCheck .ini file variable
396
Now simulator state variable
421
now simulator state variable
421
NumericStdNoWarnings .ini file variable
400
O
Operating systems supported
22
Optimize for std_logic_1164
248
Optimize_1164 .ini file variable
396
P
Packages standard
40
textio
40
Parameters, for macros
442
PathSeparator .ini file variable
400
Performance Analyzer
119
%in field
125
%parent field
126
%under field
125
commands
131
getting started
121
hierarchical profile
123
interpreting data
122
name field
125
profile report command
129
ranked profile
126
report option
129
setting preferences
130
statistical sampling
120
ModelSim EE/SE User’s Manual
view_profile command
123
view_profile_ranked command
124
viewing results
123
PLI see Verilog PLI
PLIOBJS environment variable
392
PlotFilterResolution simulator control variable
412
Ports
VHDL and Verilog
109
Preferences setting preferences from the command line
418
performance analyzer preferences
130
setting preferences with the GUI window fonts and colors
412
,
418
window sizes and locations
412
,
418
Process window (see also, Windows)
189
Process without a wait statement
247
Processes displayed in Dataflow window
170
values and pathnames in Variables window
209
profile report command
129
Project files compile a project
49
creating a project
46
modelsim.ini
default to VHDL93
406
environment variables
403
hierarchial library mapping
404
opening VHDL files
406
to specify a startup file
404
turning off arithmetic warnings
405
turning off assertion messages
405
using to create a transcript file
404
using to define force command default
405
using to delay file opening
406
modelsim.mpf
43
project definition
44
modifying a project
49
open a project
49
project operations
45
simulating a project
49
’protect compiler directive
443
Q
Quick Start
264
Quick Start guide
264
Quiet .ini file variable (VCOM)
396
Quiet .ini file variable (VLOG)
397
R
Radix specifying in List window
182
specifying in Signals window
195
Ranked profile
126
Rebuilding supplied libraries
41
reconstruct RTL-level design busses
145
Records changing values of
209
Refreshing library images
41
Register variables adding to the Wave and List windows
197
displaying values in Signals window
192
saving values as binary log file
197
viewing waveforms
212
Resolution .ini file variable
400
resolution simulator state variable
421
RunLength .ini file variable
400
S
ScalarOpts .ini file variable
397
SDF
Errors and warnings
283
Instance specification
282
interconnect delays
293
mixed VHDL and Verilog designs
293
troubleshooting
294
Verilig rounded timing values
292
Verilog
$sdf_annotate system task
286
ModelSim EE/SE User’s Manual Index -
491
optional conditions
292
optional edge specifications
291
SDF to Verilog construct matching
287
Verilog SDF annotation
286
VHDL
Resolving errors
285
SDF to VHDL generic matching
284
Searching for values and finding names in windows
154
List window signal values, transitions, and names
184
text strings in the List window
184
text strings in the Wave window
231
waveform signal values, edges and names
231
searchLog simulator command
147
Shortcuts command history
425
command line caveat
425
List window
187
,
424
text editing
167
,
426
Wave window
237
,
423
Show source lines with errors
247
Show_source .ini file variable (VCOM)
395
Show_source .ini file variable (VLOG)
397
Show_VitalChecksWarning .ini file variable
395
Show_Warning1 .ini file variable
395
Show_Warning2 .ini file variable
395
Show_Warning3 .ini file variable
396
Show_Warning4 .ini file variable
396
Signal transitions searching for
235
Signals adding to a log file
197
adding to the Wave and List windows
197
applying stimulus to
195
combining into a user-defined bus
155
displaying in Dataflow window
170
displaying values in Signals window
192
forcing signal and net values
195
saving values as binary log file
197
selecting signal types to view
195
492
- Index viewing waveforms
212
Signals window (see also, Windows)
192
Simulating applying stimulus
see also VSIM command, force
applying stimulus to signals and nets
195
applying stimulus with textio
58
batch mode
440
command-line mode
440
Mixed Verilog and VHDL Designs compilers
108
libraries
108
Verilog parameters
109
Verilog state mapping
110
VHDL and Verilog ports
109
VHDL generics
108
projects
49
saving waveform as a Postscript file
238
setting default run length
261
setting iteration limit
261
setting time resolution
252
Verilog delay modes
81
even order issues
76
hazard detection
77
resolution limit
75
XL compatible simulator options
78
Verilog designs
74
VHDL designs
53
invoking code coverage
54
viewing results in List window
174
Simulation and Compilation
Verilog
64
–
106
VHDL
51
–
61
Sorting sorting HDL items in VSIM windows
154
Source code source code security
443
viewing
200
Source directory, setting from source window
201
Source files referencing with location maps
449
ModelSim EE/SE User’s Manual
Source window (see also, Windows)
200
SourceDir simulator control variable
412
SourceMap simulator control variable
412
Src_Files .mpf file variable
402
Startup macro in the modelsim.ini file
400
startup macro in command-line mode
441
using a startup file
404
Startup .ini file variable
400
Startup macros
404
Status bar
Main window
167
std .ini file variable
395
std_developerskit .ini file variable
395
StdArithNoWarnings .ini file variable
400
STDOUT environment variable
392
Structure window (see also, Windows)
206
Symbolic link to design libraries (UNIX)
39
synopsys .ini file variable
395
System initialization
43
T
Tcl
367
–
381
, ??–
381
command separator
375
command substitution
374
evaluation order
375
history shortcuts
425
Man Pages in Help menu
164
relational expression evaluation
375
variable substitution
338
,
376
Tcl command syntax
370
Text editing, see Editing
Text strings finding in the List window
184
finding in the Wave window
231
TextIO package
51
alternative I/O files
58
containing hexadecimal numbers
57
dangling pointers
57
ENDFILE function
58
ModelSim EE/SE User’s Manual
ENDLINE function
58
file declaration
55
implementation issues
56
providing stimulus
58
standard input
56
standard output
56
WRITE procedure
56
WRITE_STRING procedure
57
Time time as a simulator state variable
420
time resolution as a simulator state variable
421
TMPDIR environment variable
392
Tool bar
Main window
165
Wave window
221
Top_DUs .mpf file variable
402
Tracing HDL items with the Dataflow window
172
TranscriptFile .ini file variable
400
Tree windows
VHDL and Verilog items in
155
viewing the design hierarchy
157
Triggers, setting in the List window
177
,
456
U
Unbound Component
247
UnbufferedOutput .ini file variable
401
UpCase .ini file variable
397
Use 1076-1993 language standard
246
Use clause specifying a library
40
Use explicit declarations only
246
UserTimeUnit .ini file variable
401
V
Values of HDL items
204
Variable settings report
403
Variables
64
Variables window (see also, Windows)
209
Variables, HDL
Index -
493
changing value of with the GUI
209
Variables, referencing loading order at ModelSim startup
419
reading variable values from the .ini file
403
shared objects
LD_LIBRARY_PATH, and SHLIB_PATH
299
MGC_HOME, and MGC_WD
299
simulator state variables iteration number
420
name of entity or module as a variable
420
resolution
420
simulation time
420
Variables, setting environment variables
391
VCD files extracting the proper stimulus
338
from VHDL source to VCD output
340
VCD system tasks
338
Verilog capturing port driver data with -dumpports
344
cell libraries
80
compiler directives
87
compiling design units
65
compiling with XL ’uselib compiler directive
72
component declaration
114
creating a design library
65
instantiation criteria
112
instantiation of VHDL design units
116
library usage
68
mapping states in mixed designs
110
mixed designs with VHDL
107
parameters
109
SDF annotation
286
sdf_annotate system task
286
simulating
74
delay modes
81
event order issues
76
XL compatible options
78
simulation hazard detection
77
simulation resolution limit
75
SmartModel interface
357
source code viewing
200
system tasks
82
XL compatible compiler options
70
XL compatible routines
104
XL compatible system tasks
85
verilog .ini file variable
395
Verilog PLI
90
–
106
specifying the PLI file to load
95
support for VHDL objects
100
Veriuser .ini file variable
401
VHDL compiling design units
52
creating a design library
52
delay file opening
406
Dependency checking
53
file opening delay
406
Hardware Model interface
360
instantiation from Verilog
116
instantiation of Verilog
108
library clause
40
mixed designs with Verilog
107
object support in PLI
100
simulating
53
SmartModel interface
348
source code viewing
200
timing check disabling
54
VHDL93 .ini file variable
395
view_profile command
123
view_profile_ranked command
124
Viewing design hierarchy
155
virtual hide command
145
Virtual objects
144
virtual functions
146
virtual regions
146
virtual signals
145
virtual types
147
virtual region command
146
Virtual regions reconstruct the RTL Hierarchy in gate level design
146
virtual save command
145
virtual signal command
145
494
- Index ModelSim EE/SE User’s Manual
Virtual signals reconstruct RTL-level design busses
145
reconstruct the original RTL hierarchy
145
virtual hide command
145
VITAL compiling and simulating with accelerated VITAL packages
61
compliance warnings
60
obtaining the specification
59
VITAL packages
59
VSIM commands searchLog
147
W
Warnings turning off warnings from arithmetic packages
405
Wave window (see also, Windows)
212
WaveSignalNameWidth .ini file variable
401
Windows change window fonts and colors
413
finding HDL item names
154
opening multiple copies
154
opening with the GUI
161
save window sizes and locations
413
searching for HDL item values
154
adding buttons
265
Dataflow window
170
tracing signals and nets
172
List window
174
adding HDL items
180
adding signals with a log file
197
examining simulation results
183
formatting HDL items
181
locating time markers
154
saving to a file
188
setting display properties
177
Main window
158
status bar
167
text editing
167
,
426
time and delta display
167
tool bar
165
Process window
189
displaying active processes
189
specifying next process to be executed
189
viewing processing in the region
189
Signals window
192
VHDL and Verilog items viewed in
192
Source window
200
text editing
167
,
426
viewing HDL source code
200
Structure window
206
HDL items viewed in
206
instance names
207
selecting items to view in Signals window
192
VHDL and Verilog items viewed in
206
viewing design hierarchy
206
Variables window
209
displaying values
209
VHDL and Verilog items viewed in
209
Wave window
212
adding HDL items
223
adding signals with a log file
197
changing display range (zoom)
235
cursor measurements
234
locating time cursors
154
searching for HDL item values
231
setting display properties
230
using time cursors
233
zoom options
235
zooming
235
Work_Libs .mpf file variable
402
Z
Zero-delay loop, detecting infinite
448
Zoom from Wave toolbar buttons
235
from Zoom menu
235
options
235
with the mouse
236
with VSIM commands 236
ModelSim EE/SE User’s Manual Index -
495
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