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Počítače a elektronika Software Model Technology Special EE/SE Uživatelská příručka

Getting Started. Model Technology Special EE/SE, Elite EE/SE

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Getting Started

During sampling, the Samples field in the footer of the main VSIM window displays the number of profiling samples collected, and each sample becomes one data point in the simulation profile.

Getting Started

Performance analysis occurs during the ModelSim run command and is displayed graphically as a profile of simulator performance. To enable the Performance

Analyzer, use the profile on command at the VSIM prompt. After this command is executed, all subsequent run commands will have profiling statistics gathered for them. With the Performance Analyzer enabled and a run command initiated, the simulator will provide a message indicating that profiling has started.

The Performance Analyzer is turned off by issuing the profile off command to the

VSIM prompt. Any ModelSim run commands that follow will not be profiled.

Profiling results are cumulative. Therefore, each run command performed with profiling ON will add new information to the data being gathered. To clear this data, issue the profile clear command to the VSIM prompt.

ModelSim EE/SE User’s Manual ModelSim SE Performance Analyzer

7-121

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Obsah

Software License Agreement

3

Model Technology Software License

ModelSim software versions documented in this manual

Sections in this document

What is an "HDL item"

26

Where to find our documentation

27

Download a free PDF reader with Search

28

Online References - www.model.com

Design library contents

32

Design unit information

32

Design library types

32

Library management commands

33

Working with design libraries

33

Creating a library

33

Viewing and deleting library contents

35

Assigning a logical name to a design library

37

Moving a library

39

Specifying the resource libraries

40

VHDL resource libraries

40

Predefined libraries

40

Alternate IEEE libraries supplied

41

Rebuilding supplied libraries

41

Regenerating your design libraries

41

Verilog resource libraries

INI and MPF file comparison

44

The [Project] section in the .mpf file

Working with a Project

Compiling VHDL designs

52

Creating a design library

52

Invoking the VHDL compiler

52

Dependency checking

53

Simulating VHDL designs

53

Invoking the simulator from the Main window

53

Invoking Code Coverage with vsim

54

Using the TextIO package

55

Syntax for file declaration

55

Using STD_INPUT and STD_OUTPUT within ModelSim

56

TextIO implementation issues

56

Writing strings and aggregates

56

Reading and writing hexadecimal numbers

Using alternative input/output files

58

Providing stimulus

58

Obtaining the VITAL specification and source code

59

VITAL packages

59

ModelSim VITAL compliance

59

VITAL compliance checking

60

Compiling and Simulating with accelerated VITAL packages

Incremental compilation

66

Library usage

68

Verilog-XL compatible compiler options

70

Verilog-XL `uselib compiler directive

72

Simulation

74

Invoking the simulator

75

Simulation resolution limit

75

Event order issues

76

Verilog-XL compatible simulator options

78

Cell Libraries

80

SDF timing annotation

IEEE Std 1364-1995 system tasks

82

Verilog-XL compatible system tasks

85

Compiler Directives

87

IEEE Std 1364-1995 compiler directives

88

Verilog-XL compatible compiler directives

89

Using the Verilog PLI

90

Registering PLI applications

90

Compiling and linking PLI applications

92

The callback reason argument

97

The sizetf callback function

99

Object handles

99

Third party PLI applications

99

Support for VHDL objects

100

IEEE Std 1364 ACC routines

101

IEEE Std 1364 TF routines

103

Verilog-XL compatible routines

104

PLI tracing

105

Separate compilers, common libraries

VHDL and Verilog ports

109

Verilog states

110

VHDL instantiation of Verilog design units

112

Verilog instantiation criteria

112

Component declaration

112

vgencomp component declaration

114

Verilog instantiation of VHDL design units

116

VHDL instantiation criteria

116

SDF annotation

117

Introducing Performance Analysis

120

A Statistical Sampling Profiler

120

Getting Started

121

Interpreting the data

122

Viewing Performance Analyzer Results

123

Interpreting the Name Field

125

Interpreting the %Under and %In Fields

125

Differences in the Ranked and Hierarchical Views

126

Ranked/Hierarchical Window Features

128

The report option

129

Setting preferences with Tcl variables

130

Performance Analyzer commands

131

Enabling Code Coverage

134

The coverage_summary window

136

Coverage Summary window preferences

137

Code Coverage commands

138

Multiple logfiles and datasets

139

Opening and viewing datasets

140

Using datasets with ModelSim commands

142

Restricting the dataset prefix display

143

Virtual Objects (User-defined buses, and more)

Logfile and virtual commands reference table

Quick access toolbars

Automatic window updating

153

Finding names, searching for values, and locating cursors

154

Sorting HDL items

154

Multiple window copies

154

Menu tear off

154

Customizing menus and buttons

155

Combine signals into a user-defined bus

155

Tree window hierarchical view

155

Main window

158

The Main window menu bar

159

The Main window tool bar

165

The Main window status bar

167

Editing the command line, the current source file, and notepads

167

Dataflow window

170

The Dataflow window menu bar

171

Tracing HDL items with the Dataflow window

172

Saving the Dataflow window as a Postscript file

173

List window

174

HDL items you can view

174

The List window menu bar

175

Setting List window display properties

177

Adding HDL items to the List window

180

Editing and formatting HDL items in the List window

181

Examining simulation results with the List window

183

Finding items by name in the List window

184

Searching for item values in the List window

184

Setting time markers in the List window

186

List window keyboard shortcuts

187

Saving List window data to a file

188

Process window

189

The Process window menu bar

190

Signals window

192

The Signals window menu bar

193

Selecting HDL item types to view

195

Forcing signal and net values

195

Adding HDL items to the Wave and List windows or a logfile

197

Finding HDL items in the Signals window

198

Defining clock signals

198

Source window

200

The Source window menu bar

201

The Source window tool bar

203

Editing the source file in the Source window

204

Checking HDL item values and descriptions

204

Setting Source window options

205

Structure window

206

The Structure window menu bar

207

Variables window

209

The Variables window menu bar

HDL items you can view

216

The Wave window menu bar

217

Wave window tool bar

220

Adding HDL items in the Wave window

223

Combining and grouping items in the Wave window

225

Editing and formatting HDL items in the Wave window

226

Setting Wave window display properties

230

Sorting a group of HDL items

231

Finding items by name or value in the Wave window

231

Searching for item values in the Wave window

231

Using time cursors in the Wave window

233

Zooming - changing the waveform display range

235

Wave window keyboard shortcuts

237

Printing and saving waveforms

238

Compiling with the graphic interface

244

Locating source errors during compilation

245

Setting default compile options

245

Simulating with the graphic interface

251

Design selection page

252

VHDL settings page

254

Verilog settings page

256

SDF settings page

258

Setting default simulation options

The GUI Expression Builder

272

The FPGA Library Manager

274

Graphic interface commands

277

Customizing the interface

279

Specifying SDF files for simulation

282

Instance specification

282

SDF specification with the GUI

SDF to VHDL generic matching

The $sdf_annotate system task

286

SDF to Verilog construct matching

287

Optional edge specifications

291

Optional conditions

292

Rounded timing values

292

SDF for Mixed VHDL and Verilog Designs

Specifying the wrong instance

294

Mistaking a component or module name for an instance label

295

Forgetting to specify the instance

295

Obtaining the SDF specification

296

Using the VHDL FLI

298

Using the VHDL FLI with foreign architectures

298

Using the VHDL FLI with foreign subprograms

300

Using checkpoint/restore with the FLI

305

Support for Verilog instances

308

Support for Windows platforms

308

FLI function descriptions

309

Mapping to VHDL data types

328

VHDL FLI examples

330

Compiling and linking FLI applications

331

Windows NT/95/98 platforms

IBM RISC/6000 platform

333

FLI tracing

334

The purpose of tracing files

334

Invoking a trace

334

ModelSim VCD commands and VCD tasks

338

Resimulating a VHDL design from a VCD file

338

Extracting the proper stimulus for bidirectional ports

338

Specifying a filename and state mappings

339

Creating the VCD file

339

A VCD file from source to output

340

VHDL source code

340

VCD simulator commands

341

VCD output

341

Capturing port driver data with -dumpports

344

Supported TSSI states

Example VCD output from -dumpports

346

VHDL SmartModel interface

348

Creating foreign architectures with sm_entity

Verilog SmartModel interface

357

LMTV usage documentation

357

Linking the LMTV interface to the simulator

357

Compiling Verilog shells

357

VHDL Hardware Model interface

360

Creating foreign architectures with hm_entity

361

Vector ports

364

Hardware model commands

366

Tcl features within ModelSim

Tcl online references

Multiple-line commands

375

Evaluation order

375

Tcl relational expression evaluation

375

Variable substitution

ModelSim Tcl time commands

Tcl examples - UNIX only

380

ModelSim worldwide contacts

383

Technical support - by telephone

384

Mentor Graphics customers In North America

384

Mentor Graphics customers outside North America

384

Model Technology customers worldwide

384

Technical support - electronic support services

384

Mentor Graphics customers

384

Model Technology customers

385

Technical support - other channels

386

Updates

386

Mentor customers: getting the latest version via FTP

386

Model Technology customers: getting the latest version via FTP

386

FLEXlm Licenses

386

Where to obtain your license

386

If you have trouble with licensing

387

All customers: ModelSim licensing

387

All customers: maintenance renewals and licenses

387

All customers: license transfers and server changes

387

Additional licensing details

387

Variable settings report

390

Personal preferences

390

Returning to the original ModelSim defaults

390

Environment variables

391

ModelSim Environment Variables

391

Setting environment variables in Windows

392

Referencing environment variables within ModelSim

393

Removing temp files (VSOUT)

394

Preference variables located in INI and MPF files

394

[Library] library path variables

395

[vcom] VHDL compiler control variables

395

[vlog] Verilog compiler control variables

397

[vsim] simulator control variables

398

[lmc] Logic Modeling variables

401

[Project] project file section (MPF files only)

402

Setting variables in INI / MPF files

402

Reading variable values from the INI file

Preference variables located in TCL files

406

User-defined variables

407

Viewing the default preference file (pref.tcl)

407

Preference variable arrays

407

Main window preference variables

411

The Main window uses preference variables similar to other ModelSim window to conrol colors and f...

411

Individual preference variables

411

The addons variable

412

Setting Tcl preference variables

412

More preferences

419

Preference variable loading order

419

Simulator state variables

420

Referencing simulator state variables

421

Wave window keyboard shortcuts

423

List window keyboard shortcuts

424

Command shortcuts

425

Command history shortcuts

425

Editing the command line, the current source file, and notepads

426

Right mouse button

427

Starting the license server daemon

430

Locating the license file

430

Controlling the license file search

430

Manual start

430

Automatic start at boot time

431

What to do if another application uses FLEXlm

431

Format of the license file

432

Format of the daemon options file

432

License administration tools

How to use checkpoint/restore

438

The difference between checkpoint/restore and restarting

439

Using macros with restart and checkpoint/restore

439

Running command-line and batch-mode simulations

Passing parameters to macros

442

Source code security and -nodebug

443

Saving and viewing waveforms

445

Setting up libraries for group use

445

Bus contention checking

446

Bus float checking

447

Design stability checking

447

Toggle checking

447

Detecting infinite zero-delay loops

448

Referencing source files with location maps

449

Using location mapping

449

Pathname syntax

450

How location mapping works

450

Mapping with Tcl variables

450

Accelerate simulation by locking memory under HP-UX 10.2

451

Modeling memory in VHDL

452

Setting up a List trigger with Expression Builder

456

New features

459

GUI changes and new features

461

New file types

461

Command and variable changes

462

Documentation changes

463

Find 5.2 features in the 5.3 interface

465

Main window toolbar buttons and menu selections

466

Main window menu changes

Library menu selections

470

Run menu selections

471

Options menu selections

472

Window menu selections

473

Help menu selections

474

List window menu changes

475

Prop menu selections

475

Process window menu changes

476

File menu selections

476

Signals window menu changes

477

Edit menu selections

477

Structure window menu changes

Variables window menu changes

480

Edit menu selections

480

Wave window menu changes

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