Chapter 1: Hardware Design Using System Generator have detailed knowledge of the underlying FPGA details. However, when it makes sense to implement an algorithm using basic functions (e.g., adder, register, memory), System
Generator allows you to exploit your FPGA knowledge while reducing the clerical tasks of managing all signals explicitly.
System Generator library blocks and the mapping from Simulink to hardware are described in detail in subsequent topics of this documentation. There is a wealth of detailed information about FPGAs that can be found online at http://support.xilinx.com
, including data books, application notes, white papers, and technical articles.
Note to the DSP Engineer
System Generator extends Simulink to enable hardware design, providing high-level abstractions that can be automatically compiled into an FPGA. Although the arithmetic abstractions are suitable to Simulink (discrete time and space dynamical system simulation), System Generator also provides access to features in the underlying FPGA.
The more you know about a hardware realization (e.g., how to exploit parallelism and pipelining), the better the implementation you’ll obtain. Using IP cores makes it possible to have efficient FPGA designs that include complex functions like FFTs. System Generator also makes it possible to refine a model to more accurately fit the application.
Scattered throughout the System Generator documentation are notes that explain ways in which system parameters can be used to exploit hardware capabilities.
Note to the Hardware Engineer
System Generator does not replace hardware description language (HDL)-based design, but does makes it possible to focus your attention only on the critical parts. By analogy, most DSP programmers do not program exclusively in assembler; they start in a higherlevel language like C, and write assembly code only where it is required to meet performance requirements.
A good rule of thumb is this: in the parts of the design where you must manage internal hardware clocks (e.g., using the DDR or phased clocking), you should implement using
HDL. The less critical portions of the design can be implemented in System Generator, and then the HDL and System Generator portions can be connected. Usually, most portions of a signal processing system do not need this level of control, except at external interfaces.
System Generator provides mechanisms to import HDL code into a design (see Importing
HDL Modules ) that are of particular interest to the HDL designer.
Another aspect of System Generator that is of interest to the engineer who designs using
HDL is its ability to automatically generate an HDL testbench, including test vectors. This aspect is described in the topic
HDL Testbench .
Finally, the hardware co-simulation interfaces described in the topic
Using Hardware Co-
Simulation allow you to run a design in hardware under the control of Simulink, bringing
the full power of MATLAB and Simulink to bear for data analysis and visualization.
Design Flows using System Generator
System Generator can be useful in many settings. Sometimes you may want to explore an algorithm without translating the design into hardware. Other times you might plan to use a System Generator design as part of something bigger. A third possibility is that a System
Generator design is complete in its own right, and is to be used in FPGA hardware. This topic describes all three possibilities.
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System Generator for DSP User Guide
UG640 (v11.4) December 2, 2009
