Bitstream Compilation
Additional Settings
You may access additional compilation settings specific to Bitstream compilation by clicking on the Settings... button when Bitstream is selected as the compilation type in the
System Generator block dialog box. Parameters specific to the Bitstream Settings dialog box include:
•
Import Top-level Netlist: Allows you to specify your own top-level netlist into which the System Generator portion of the design is included as a module. You may choose to import your own top-level netlist if you have a larger design that instantiates the
System Generator clock wrapper level as a component. Refer to the
Compilation
Results
topic for more information on the clock wrapper level. This top-level netlist is included in the bitstream file that is generated during compilation. Selecting this checkbox enables the edit fields Top-level Netlist File (EDIF or NGC) and Search Path for Additional Netlist and Constraint Files.
♦
Top-level Netlist File (EDIF or NGC)
: Specifies the name and location of the toplevel netlist file to include during compilation. Note that any HDL components that are used by your top-level (including the top-level itself) must have been previously synthesized into netlist files.
♦
Search Path for Additional Netlist and Constraint Files
: Specifies the directory where System Generator should look for additional netlist and constraint files that go along with the top-level netlist file. System Generator copies all netlist
(e.g., .edn, .edf, .ngc) and constraints files (e.g., .ucf, .xcf, .ncf) into the implementation directory when this directory is specified. If you do not specify a directory, System Generator will only copy the netlist file specified in the Top-
level Netlist File
field.
•
Specify Alternate Clock Wrapper
: Allows you to substitute your own clock wrapper logic in place of the clock wrapper HDL System Generator produces. The clock wrapper level is the top-level HDL file that is created for a System Generator design, and is responsible for driving the clock and clock enable signals in that design.
Sometimes you may want to supply your own clock wrapper, for example, if your design uses multiple clock signals, or if you have a board-specific hardware you would like your design to interface to.
Note:
The name of the alternate clock wrapper file must be named <design>_cw.vhd or
<design>_cw.v
or it will not be used during bitstream generation.
•
XFLOW Option Files
: When a design is compiled for System Generator hardware cosimulation, the command line tool, XFLOW, is used to implement and configure your design for the selected FPGA platform. XFLOW defines various flows that determine the sequence of programs that should be run on your design during compilation.
There are typically multiple flows that must be run in order to achieve the desired output results, which in the case of hardware co-simulation targets, is a configuration bitstream.
♦
Implementation Phase (NBDBuild, MAP, PAR, TRACE)
: Specifies the options file that is used by the implement flow type. By default, System Generator will use the implement options file that is specified by the compilation target.
♦
Configuration Phase (BitGen)
: Specifies the options file that is used by the configuration flow type. By default, System Generator will use the configuration options file that is specified by the compilation target.
System Generator for DSP User Guide
UG640 (v11.4) December 2, 2009 www.xilinx.com
347