Importing a System Generator Design into a Bigger System
Importing a System Generator Design into a Bigger System
A System Generator design is often a sub-design that is incorporated into a larger HDL design. This topic shows how to embed two System Generator designs into a larger design and how VHDL created by System Generator can be incorporated into the simulation model of the overall system.
Starting with Release 10.1, System Generator introduces a new integration flow between
System Generator (Sysgen) and Project Navigator (ProjNav). This first phase of integration concentrates on the following areas:
•
Allows you to add a System Generator design as a sub-level to a larger design
•
Consolidates and associates System Generator constraints to the top-level design
•
Enables you to perform certain design iterations between Project Navigator and the
System Generator design
HDL Netlist Compilation
Selecting the HDL Netlist compilation target from the System Generator token instructs
System Generator to generate HDL along with other related files such as NGC files and
EDIF files that implement the design. In addition, System Generator produces auxiliary files that simplify downstream processing such as bringing the design into Project
Navigator, simulating the design using an HDL simulator, and performing logic synthesis using various logic synthesis tools. See the topic
System Generator Compilation Types for
more details.
Starting with Release 10.1, the System Generator project information is encapsulated in the file <design_name>_cw.sgp or <design_name>_mcw.sgp depending on which clocking option is selected. This topic shows how multiple System Generator designs can be included as sub-modules in a larger design.
Integration Design Rules
When a System Generator model is to be included into a larger design, the following two design rules must be followed.
Rule 1
: No Gateway or System Generator token should specify an IOB/CLK location constraint. Otherwise, the NGDBuild tool will issue the following warning:
WARNING:NgdBuild:483 - Attribute "LOC" on "clk" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.
Also, IOB timing constraints should be set to "none" in this case as well to avoid the following NGDBuild error:
NgdBuild:756 -Could not find net(s) 'gateway_out(1)' in the design.
To suppress this error, specify the correct net name or remove the constraint.
Rule 2
: If there are any I/O ports from the System Generator design that are required to be bubbled up to the top-level design, appropriate buffers should be instantiated in the toplevel HDL code.
System Generator for DSP User Guide
UG640 (v11.4) December 2, 2009 www.xilinx.com
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