Chapter 1: Hardware Design Using System Generator
The “Expose Clock Ports” Multirate Implementation
When you select this option, System Generator creates a top-level wrapper that exposes a clock port for each rate. You can then manually instantiate a clock generator outside the design to drive the clock ports.
For a detailed examination of the files produced by this option, refer to the topic
Tutorial
Example: Using the Expose Clock Ports Option .
Core Caching
System Generator uses cores produced by Xilinx CORE Generator™ (coregen) to implement parts of designs. Generating cores can be expensive, so System Generator caches previously generated ones. Before coregen is called, System Generator looks in the cache, and if the core has already been generated, System Generator reuses it.
By default, the cache is the directory $TEMP/sg_core_cache. And by default, System
Generator caches no more than 2,000 cores. When the limit is reached, System Generator deletes cached cores to make room for new ones.
Note:
Environment variables can be used to change the location of the cache and the cache size limit. The variables are described below.
Environment Variable
SGCORECACHE
SGCORECACHELIMIT
Description
Location to store cached files. Setting this variable to a string of blanks instructs System Generator not to cache cores.
Maximum number of cores to cache.
HDL Testbench
Ordinarily, System Generator designs are bit and cycle-accurate, so Simulink simulation results exactly match those seen in hardware. There are, however, times when it is useful to compare Simulink simulation results against those obtained from an HDL simulator. In particular, this makes sense when the design contains black boxes. The Create Testbench checkbox in the System Generator block makes this possible.
Suppose the design is named <design>, and a System Generator block is placed at the top of the design. Suppose also that in the block the Compilation field is set to HDL Netlist, and the Create Testbench checkbox is selected. When the Generate button is clicked,
System Generator produces the usual files for the design, and in addition writes the following:
1.
A file named <design>_tb.vhd/.v that contains a testbench HDL entity;
2.
Various .dat files that contain test vectors for use in an HDL testbench simulation.
3.
Scripts vcom.do and vsim.do that can be used in ModelSim to compile and simulate the testbench, comparing Simulink test vectors against those produced in HDL.
System Generator generates the .dat files by saving the values that pass through gateways. In the HDL simulation, input values from the .dat files are stimuli, and output values are expected results. The testbench is simply a wrapper that feeds the stimuli to the
HDL for the design, then compares HDL results against expected ones.
50
www.xilinx.com
System Generator for DSP User Guide
UG640 (v11.4) December 2, 2009
