Chapter 2: Hardware/Software Co-Design
Tutorial Example - Designing and Simulating MicroBlaze Processor
Systems
This topic shows an example on how to design and simulate a System Generator model containing a MicroBlaze™ processor. A DSP48 co-processor is developed using System
Generator. Using the EDK Processor block, you import a MicroBlaze processor, customized in Xilinx Platform Studio (XPS), into the System Generator model. You then attach the
DSP48 co-processor to the imported MicroBlaze processor through the automatic memory mapping mechanisms provided by the EDK Processor block.
This tutorial uses hardware co-simulation to simulate and verify the design. In this case, the MicroBlaze processor is compiled into hardware, while the DSP48 co-processor model is left in the System Generator diagram for software simulation. In this example, the hardware simulation and software simulation communicate with each other using the point-to-point Ethernet co-simulation technology.
This tutorial example contains the following topics:
•
Create an XPS Project
•
Create a DSP48 Co-Processor Model
•
Import an XPS Project
•
Configure Memory Map Interface
•
Write Software Programs
•
Create a Hardware Co-Simulation Block
•
Create a Testbench Model
•
Update the Co-Simulation Block with Compiled Software
•
Run the Simulation
This example uses the Xilinx Virtex®-4 ML402 Evaluation Platform.
The files used in this tutorial can be found a pathname:
<sysgen_tree>\examples\EDK\DSP48CoProcessor
, where <sysgen_tree> denotes the System Generator installation directory.
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Create an XPS Project
First of all, you will need to create a new XPS project, which contains an PLB-based UART
peripheral. A tutorial on how to create a new XPS project can be found in the topic Using
XPS .
Create a DSP48 Co-Processor Model
Copy the DSP48CoProcessorModel found in the folder
<sysgen_tree>\examples\EDK\DSP48CoProcessor
into a temporary working directory, then open the model.
The model contains a DSP48 block with the a, b, and c ports fed from three shared From
Registers with corresponding names. The op port receives signals from a multiplexer whose select line is sourced from a shared From FIFO named instr.
The output port p of the DSP48 block is sliced and fed into another two shared To Resigers: the top 16 bits into the overflow register and the bottom 32 bits into the result register.
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Chapter 2: Hardware/Software Co-Design
Import the XPS Project
In this step, you import an XPS project that contains a MicroBlaze processor into the DSP48
Co-Processor model. Double click on the subsystem called Processor Subsystem and look into it. In that subsystem, you will find a System Generator token and a blue text box as the place holder for an EDK Processor block. Open the System Generator block set and drag an
EDK Processor block from the Index library into the Processor Subsystem. Your augmented subsystem should look like the one shown below:
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You will now configure the EDK Processor block to import the XPS project. The import process will make changes to the XPS project. Thus, ensure that the XPS project is not currently opened by Xilinx Platform Studio before importing.
Double click on the processor block to bring up the block dialog box. In the Configure
processor for
drop-down menu, select HDL netlisting. The Import… button is enabled as a result of the selection.
Note that the Import… button is disabled when the processor is configured for EDK pcore
generation. In EDK pcore generation mode, it is expected that you will create a pcore in
System Generator and export it to be used in another XPS project. In this case, the processor is not instanced inside the EDK Processor block. In HDL netlisting mode, it is expected that you import an XPS project into the System Generator model and netlist it with other System Generator blocks.
If no XPS project is ever imported, configuring the processor for HDL netlisting will automatically trigger the launching of the XPS Import Wizard. The XPS Import Wizard can be launched manually by pressing the Import… button.
In the pop-up file selection dialog, browse to the XPS project created in earlier steps. The import process starts once a XPS project file (xmp file) is selected. The import process copies necessary files into the XPS project and changes the project accordingly to allow the
MicroBlaze processor to communicate with the System Generator model.
Note that if there is any software applications contained by the imported XPS project, they are not compiled during import. www.xilinx.com
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Configure Memory Map Interface
Re-open the dialog box of the EDK Processor block. Add all the shared memories in the model to the processor's memory map by selecting <all> in the Available memories pulldown menu and then press the Add button. The EDK Processor block dialog box should look like the following screenshot. Dismiss the dialog box by clicking the OK button at the bottom.
Write Software Programs
You will write software programs running on MicroBlaze processor to read from and write to the shared memories. Re-open the XPS project in Xilinx Platform Studio. Create a new software application called MyProject. Make sure that the MyProject software application is marked for download into BRAM while the other software applications are unmarked.
Refer to the topic Using XPS
on how to add a new software application to an EDK project.
Create a new source code file MyProject.c for MyProject and open it in the XPS code editor.
The above figure shows a portion of the System Assembly View of the XPS project in Xilinx
Platform Studio. A sg_plbiface peripheral is automatically added to an XPS project after it is successfully imported into System Generator. The sg_plbiface peripheral connects the PLB bus attached to the imported MicroBlaze processor to the System Generator model through a memory-mapped interface, and to capture information on how to generate the
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Chapter 2: Hardware/Software Co-Design corresponding device software drivers. Right click on sg_plbiface in the System Assembly
View to see its API documentation.
Follow the instructions in the API documentation to include the following header file and initialize the software driver in MyProject.c.
#include "sg_plbiface.h" xc_iface_t *iface;
// initialize the software driver xc_create(&iface, &SG_PLBIFACE_ConfigTable[0]);
Before reviewing the code to run on the processor, first consider how to write data to the a register on the model. Look at the DSP48 Co-Processor model. Recall that the a port of the
DSP48 block is driven by the output of a shared register by the same name. You want to write a value to that shared register from with-in MicroBlaze processor code. By referring to the driver API, you can see that the shared memory called a is a “To Register” memory type with xc_to_reg_t access data type, which contains the following data fields: typedef struct {
xc_w_addr_t din;
uint32_t n_bits;
uint32_t bin_pt;
} xc_to_reg_t;
Once the software driver is initialized, din stores the memory-mapped address of the din port of the shared memory a, while n_bits and bin_pt store the number of bits and binary point information.
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So in order to write a value to the a shared register, you need to first obtain its settings through xc_get_shmem and thus:
xc_to_reg_t *toreg_a;
xc_get_shmem(iface, "a", (void **) &toreg_a);
Note:
Calling xc_get_shmem is expensive. You should cache the returned toreg_a for later use and avoid calling xc_get_shmem multiple times in a program.
You can then use the following single-word write access function to write to the a shared register:
// -- Set the a port register to 2
xc_write(iface, toreg_a->din, 2); www.xilinx.com
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The full code of MyProject.c is located at the following pathname:
<sysgen_tree>\examples\EDK\DSP48CoProcessor\MyProject.c
Copy and paste the above code into MyProject.c.
Create a Hardware Co-Simulation Block
The complete Simulink model can be simulated through hardware co-simulation. Make sure that the shared memories are added into the Memory Maps window and the EDK
Processor block is configured for HDL netlisting. These are required for hardware cosimulation.
Open the dialog box of the System Generator token in the same subsystem as the EDK
Processor block. You generate the hardware co-simulation block from this level of the model so that only the imported MicroBlaze processor runs in hardware while the rest of the design is kept in Simulink for software simulation.
Under the Compilation menu select Hardware Co-simulation > ML402 > Ethernet >
Point-to-point
. Next, press the Generate button to begin the compilation process. This may take some time. Upon completion, a hardware co-simulation block is created that contains a MicroBlaze processor.
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Create a Testbench Model
A testbench model will be created to use the co-simulation block created in the previous step. Open the DSP48CoProcessor model and delete the Processor Subsystem. Copy the
Processor Subsystem hwcosim block you just generated into the DSP48CoProcessor model. Save the model as DSP48CoProcessor_testbench.mdl.
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Update the Co-Simulation Block with Compiled Software
Return to the testbench model. Double click on the Processor Subsystem hwcosim block to bring up the dialog box shown above. To compile the software contained in the XPS project listed in the Software tab and load it into the hardware co-simulation bitstream, click the button labeled Compile and update bitstream.
Since Point-to-point Ethernet co-simulation is chosen, you need to configure the Ethernet interface and also the Configuration interface of the Processor Subsystem hwcosim block.
Select a valid Host interface for your Ethernet communications, and set the configure interface to Point-to-point Ethernet. Refer to the topic
Using Hardware Co-Simulation
for more usage information of the hardware co-simulation block.
Run the Simulation
Before starting the simulation, you need to set up a terminal connected to the COM port of your computer. This allows for text inputs and outputs to be read from and written to the
MicroBlaze processor through the RS232 port.
Open up your favorite terminal program. Windows comes with a Hyperterminal application, which can be found in Start > All Programs > Accessories > Communications
> Hyperterminal. Set up the terminal program to listen to the COM port that you have wired your RS232 to.
Configure your terminal as follows:
•Baud rate = 115200
•Data = 8 bits
•Parity = none
•Stop = 1 bit
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