Automatic Code Generation
Resource Estimation
System Generator supplies tools that estimate the FPGA hardware resources needed to implement a design. Estimates include numbers of slices, lookup tables, flip-flops, block memories, embedded multipliers, I/O blocks and tristate buffers. These estimates make it easy to determine how design choices affect hardware requirements. To estimate the resources needed for a subsystem, drag a Resource Estimator block into the subsystem, double-click on the estimator, and press the Estimate button.
Automatic Code Generation
System Generator automatically compiles designs into low-level representations. The ways in which System Generator compiles a model can vary, and depend on settings in the
System Generator block. In addition to producing HDL descriptions of hardware, the tool generates auxiliary files. Some files (e.g., project files, constraints files) assist downstream tools, while others (e.g., VHDL testbench) are used for design verification.
Compiling and Simulating Using the System Generator Block
Compilation Results
HDL Testbench
Describes how to use the System Generator block to compile designs into equivalent low-level HDL.
Describes the low-level files System Generator produces when HDL Netlist is selected on the System
Generator block and Generate is pushed.
Describes the VHDL testbench that System Generator can produce.
System Generator for DSP User Guide
UG640 (v11.4) December 2, 2009 www.xilinx.com
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