Ethernet Hardware Co-Simulation
Point-to-Point Ethernet Hardware Co-Simulation
Point-to-point Ethernet Hardware Co-simulation provides a co-simulation interface using a raw Ethernet connection. The raw Ethernet connection refers to a Layer 2 (a.k.a. Data-
Link Layer) Ethernet connection, between a supported FPGA development platform and a host PC, with no network routing equipment along the path. By taking the advantage of the ubiquity and advancement of Ethernet technologies, the interface facilitates a convenient and high-bandwidth co-simulation to an external FPGA device.
Interface Features
The interface supports 10/100/1000 Mbps half/full duplex modes. Jumbo Frame is also supported on a Gigabit Ethernet, provided it is enabled by the underlying connection. For
FPGA device configuration, the interface supports either JTAG-based configuration over a
Xilinx Parallel Cable IV or a Xilinx Platform USB cable, or Ethernet-based configuration over the same Point-to-point Ethernet connection for co-simulation.
Note:
This co-simulation interface utilizes an evaluation version of the Ethernet MAC core. Because this is an evaluation version of the core, it will become dysfunctional after continuous, prolonged operation (e.g., around 7 hours) in the target FPGA. Operation of the core will restart with a new simulation. For more information about obtaining the full version of the core, please visit the product page at http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?key=TEMAC .
Supported FPGA Development Platforms
Development platforms that support point-to-point ethernet hardware co-simulation are listed in the topic
Ethernet-Based Hardware Co-Simulation
. Links to the appropriate platform installation instructions are also provided.
Configuring Co-Simulation Block Parameters
There are several block parameters specific to the Point-to-point Ethernet co-simulation interface. The rest of this topic describes step-by-step how to configure the parameters of the Point-to-point Ethernet co-simulation block. Refer to the topic Point-to-point Ethernet
Co-Simulation in the Xilinx Block section for details of all the block parameters.
1.
Use the Basic tab to select the appropriate clock source for the co-simulation.
Select a Clock
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2.
Use the Configuration tab to select the Configuration Method:
♦
♦
♦
♦
For the Download cable panel, choose Point-to-point Ethernet.
For JTAG-based download cables (Parallel Cable IV or Platform USB), change the cable speed if the default value is not suitable for the cable in use.
Change the Configuration timeout (ms) value only when necessary. The default value should suffice in most cases. A larger value is needed when it takes a considerable amount of time to re-establish a network connection with the FPGA platform after device configuration completes.
If there is a Video I/O daughter card attached to the ML402 platform, select Video
I/O Daughter Card (VIODC)
from the Configuration profile pulldown menu
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Ethernet Hardware Co-Simulation
3.
Use the Ethernet tab to configure the Ethernet Interface Settings:
Select an Interface
♦
From the Host interface panel, use the pulldown list to select the appropriate network interface for co-simulation.
Note:
The pull down list only shows those Ethernet-compatible network interfaces installed on the host, which support 10/100/1000 Mbps, and are currently enabled and attached to an active Ethernet segment. If the target interface is not listed as expected, examine the connection and click the Refresh button to update the list.
♦
The information box beneath the pull-down list provides the details about the selected interface. Examine the information to ensure the appropriate interface is chosen, and adjust the network settings in the operating system when necessary.
4.
Depending on which configuration method is chosen, the MAC address in the FPGA
interface
panel may need to be changed.
a.
For Point-to-point Ethernet-based configuration:
Observe the MAC address displayed on the LCD screen of the target platform when the configuration boot-loader is running. Change the FPGA MAC address in the co-
simulation block if the default value does not match the target board. Refer to Optional
Step to set the Ethernet MAC Address and the IPv4 Address
for details about assigning the MAC address on a ML402 platform.
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Note:
The MAC address must be specified using six pairs of two-digit hexadecimal number separated by colons (for example, 00:0a:35:11:22:33).
Co-Simulating the Design
After setting the block parameters appropriately, you may begin co-simulation by pressing the Simulink Start button. System Generator automates the device configuration process and transfers the design under test (DUT) into the FPGA device for co-simulation. A dialog box will be shown to describe the status of the process.
1.
The final configuration file is first generated based on the input bitstream specified in the block parameters.
2.
The final configuration file is then transferred to the target platform using the selected download cable, and used to configure the FPGA device. The progress of configuration is shown in the dialog box when the configuration is performed over a
Point-to-point Ethernet connection.
3.
Upon the completion of device configuration, the co-simulation engine re-establishes the connection to the target platform, and starts co-simulating the design.
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