Design Styles for the DSP48
DSP48 Design Techniques
Designing Filters with the DSP48
The DSP48 is an ideal block to implement FIR filters. You can examine how to use the
DSP48 block for Type 1 and Type 2 FIR filters by opening the simulink model that is located at the follwing pathname in the System Generator software tree:
.../sysgen/examples/dsp48/firs/dsp48_firs_tb.mdl
Design Techniques for Very-High Performance Designs
DSP48-based designs usually require I/O, BRAMS and SLICE logic. Typically, this associated SLICE logic is used to implement delay registers, SRL16s, muxes, counters, and control logic. Since the DSP48 block is expected to operate at speeds greater than 500 MHz, other components will also be required to operate at the same speed. This generally requires special design techniques for the non-DSP48 logic.
At 500 MHz only 2 ns is available in each clock. For V4-11 devices, roughly 300 ps are required for register clock to out and 300 ps for setup. For comparison, a LUT delay is 166 ps. Special inputs and outputs such as clock enables and DSP48 and BRAM signals generally have setup and clock to out times closer to 500 ps. With clock skew and jitter, roughly 1 ns is available for net delays. This restriction will generally allow only 1 net in each path and it must be fairly short.
There are a number of guidelines that can be used to insure the operation at DSP48 speeds.
Some of these guidelines are outlined below.
8) srl16 as control pattern generator
9) dsp48 as counter, adder
5) Limit fanout to 4-8 loads
SRL16 BRAM
DSP48
2) Extra output regs
+
1) Pipeline regs
BRAM
lut
6) Use input and output regs with
LUTs
7) Limit to 1 level of logic
+ +
3) PCOUT-PCIN b
1) use input and output regs
4) Use extra registers to cover distance greater than 20-40 slices
1.
Always use DSP48, BRAM16, FIFO16 with input, mult and output registers
2.
Use additional FF to buffer DSP48 and BRAM outputs if necessary
3.
Plan out the usage of the PCOUT-PCIN bus to allow DSP48 chaining
4.
Add registers to any path that is greater than 20 - 40 slices long
5.
Limit fanout to 32 loads located within a 20 slice distance
6.
Add output registers to any LUT-based logic
7.
Limit LUTs to 1 level or a 4:1 MUX and insure a local register for input or output
8.
Use RAMs, SRL16 to clock out control patterns instead of state machines
9.
Use DSP48 to implement counters and adders greater than 8-16 bits
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10. Use area constraints – "INST ff1* LOC = SLICE_X0Y8:SLICE_X1Y23;"
Physical Planning for DSP48-Based Designs
The DSP48 requires correct placement to achieve dense, high performance designs. While the automatic place and route tools do a good job, the best results may require manual placement of DSP48 and RAM blocks. There are several additional issues with the DSP48s.
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Cascade Routing Buses
Adjacent DSP48 blocks are connected with two local buses called PCOUT, and BCOUT.
The PCOUT bus is used to pass accumulation data from one DSP48 to the next. The
BCOUT bus is used to pass delayed B input data to the next DSP48. The DSP48 and DSP48
Macro block both support PCOUT and BCOUT buses. The use of the buses is shown in the figure above, which illustrates a pipelined 4-Tap Type 1 FIR filter.
C-Input Sharing
Each pair of DSP48s share a single C input. You should be aware of this when you do resource planning. Since the placer will not always find the most optimal placement to share C inputs, DSP48s should avoid using C inputs if possible.
Adder Trees Planning
Tree-based filter topologies are problematic for efficient DSP48 implementation. An adder tree requires isolated 2-input adders. Two input 36-bit adders can be implemented using a single DSP48, however this requires a C input and precludes the use of the multiplier. In addition, the long signals between DSP48s may require additional pipeline stages. A better approach is to convert the tree into a pipelined cascade.
Placement
Most designs will benefit from some placement of DSP48 and BRAMs. Use of area constraints to constrain LUT fabric logic placement may also be beneficial.
Signal Length Planning
At 500 MHz, signal lengths should be limited to around 20 slices. This means that long signals should have multiple pipeline stages. www.xilinx.com
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Design Styles for the DSP48
Clock Enable Planning
When using the Clock Enables clocking option, the clock enables are often the limiting path at high frequencies. This is partially due to System Generator's use of LUTs to gate clocks at the destination. To avoid clock enables in the critical path, avoid using the System
Generator upsampled and downsampled clock domains. This requires the manual use of clock enables for logic that runs at less than the system clock rate.
Place and Route Flow
•
Use the command map -timing with effort level high for both map and place
•
Use trce –v 100 to get a good sense of the failing nets and inspect the xflow/design.twr
file to understand the nature of the design's timing.
•
The file bitstream_v4.opt is available in the examples/dsp48 directory. This file can be used with the Bitstream compile target to set the PAR options mentioned above.
Synthesis Flow
•
Use Synplify Pro with retiming and pipelining enabled to avoid having to manually pipeline every LUT and signal.
•
Use Synplify Pro with the fanout limit set around 32 to avoid long net delays.
•
Open compiled projects in Synplify Pro and inspect the generated logic using the
RTL- and Gate-level views to get a good idea of what logic is being generated.
•
The file syn.pl is available in the examples/dsp48 directory. Place this file in
<sysgen_tree>/scripts
directory to modify the synthesis options in System
Generator
Logic Depth Planning
The following rules seem to allow the LUT fabric to run at 450 MHz using a -11 V4 device:
•
Only one net can be allowed in a critical path at 450 MHz. This allows a 4:1 mux to a reg a 4_input LUT to a reg or a net through a LUT directly to a DSP48
•
Counters up to 16-bits can be used, but do not use count limited counters without additional pipelining
•
If accumulators or counters are used, invert the enable line to an active-low condition to prevent a extra LUT from being inserted in the critical path
•
Any adders must have local input registers. It may be necessary to place control counters in the DSP48 to insure speed.
Fanout Planning
Avoid fanouts of more than 32 LUTs or 8 DSP48s or BRAMs. This can be avoided by inserting additional pipeline registers in these signals paths.
Register Retiming
Check retiming on delay blocks to allow them to be used as registers for pipelining. Then use Synplify Pro or XST with retiming enabled to allow the synthesis tool to move registers into optimal positions.
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Using FDATool in Digital Filter Applications
The following example demonstrates one way of specifying, implementing, and simulating a FIR filter using the FDATool block. The FDATool block is used to define the filter order and coefficients and the Xilinx Blocksets are used to implement a MAC-based
FIR filter using a single MAC (Multiply-ACcumulate) engine. The quality of frequency response is then validated by comparing it to a double-precision Simulink filter model.
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Although a single MAC engine FIR filter is used for this example, we strongly recommend that you look at the DSP Reference Library provided as a part of the Xilinx Reference
Blockset. The DSP Reference Library consists of multi-MAC, as well as, multi-channel implementation examples with variations on the type of memory used. www.xilinx.com
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