Chapter 4: Importing HDL Modules
Black Box Examples
Black Box Tutorial Example 1:
Importing a Core Generator
Module that Satisfies Black Box
HDL Requirements
Black Box Tutorial Example 2:
Importing a Core Generator
Module that Needs a VHDL
Wrapper to Satisfy Black Box
HDL Requirements
Black Box Tutorial Example 3:
Importing a VHDL Module
Describes an approach that uses the System Generator
Black Box Configuration Wizard.
Describes an approach that requires that you to provide a VHDL core wrapper. Simulation issues are also addressed.
Black Box Tutorial Example 4:
Importing a Verilog Module
Black Box Tutorial Example 5:
Dynamic Black Boxes
Black Box Tutorial Example 6:
Simulating Several Black Boxes
Simultaneously
Black Box Tutorial Exercise 7:
Advanced Black Box Example
Using ModelSim
Black Box Tutorial Example 8:
Importing, Simulating, and
Exporting an Encrypted VHDL
File
Describes how to use the Black Box block to import
VHDL into a System Generator design and how to use
ModelSim to co-simulate.
Demonstrates how Verilog black boxes can be used in
System Generator and co-simulated using ModelSim.
Demonstrates dynamic black boxes using a transpose
FIR filter black box that dynamically adjusts to changes in the widths of its inputs.
Demonstrates how several System Generator Black
Box Blocks can be co-simulated simultaneously, using only one ModelSim license while doing so.
Describes how to design a Black Box block with a dynamic port interface and how to configure a black box using mask parameters. Also, describes how to assign generic values based on input port data types and how to save black box blocks in Simulink libraries for later reuse. How to specify custom scripts for
ModelSim HDL co-simulation is also covered.
Describes how to import an encrypted VHDL file into a Black Box, simulate the design, then export the encrypted VHDL file separately from the rest of the design netlist.
Importing a Xilinx Core Generator Module
This topic describes two different ways of importing Xilinx CORE Generator™ modules, as black boxes, into System Generator. The first example shows how to import blocks
which satisfy Black Box HDL Requirements and Restrictions
. The second example shows
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how to write a VHDL wrapper to import CORE Generator™ modules as black boxes. The flow graph below illustrates the process of importing CORE generator modules.
Black Box Tutorial Example 1: Importing a Core Generator Module that
Satisfies Black Box HDL Requirements
1.
Start CORE Generator and open the the following CORE Generator project file:
<sysgen_tree>/examples/coregen_import/example1/coregen_import_e xample1.cgp
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2.
Double click the CORDIC 4.0 icon to launch the customization GUI
3.
Parameterize and generate the CORDIC 4.0 core with component name cordic_sincos
, a functional Selection of Sin and Cos and the remaining options set to be the default values as shown below:
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4.
Click Generate. Core Generator produces the following files after generation:
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♦ cordic_sincos.ngc
cordic_sincos.vhd
cordic_sincos.vho
cordic_sincos.xco
: Implementation netlist
: VHDL wrapper for behavioral simulation
: Core instantiation template
: Parameters selected for core generation
5.
Start Simulink and open the design file
(<sysgen_tree>/examples/coregen_import/example1/coregen_import_ example1.mdl
)
6.
Drag and drop the black box from the Xilinx "Basic Elements" library into the model coregen_import_example1.mdl
. Select cordic_sincos.vhd for the top-level
HDL file and click Open.
7.
Connect the input and output ports of the black box to the open wires.
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8.
Open the cordic_sincos_config.m file, and add the EDIF netlist to the black box file list as shown below. This file will get included as part of the System Generator netlist for the design when it is netlisted.
9.
Open the black box parameterization GUI and select ISE Simulator for the simulation mode.
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10. Press the Simulate button to compile and co-simulate the CORDIC core using the ISE simulator. The simulation results are as shown below.
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Black Box Tutorial Example 2: Importing a Core Generator Module that
Needs a VHDL Wrapper to Satisfy Black Box HDL Requirements
1.
Start Core Generator and open the Core Generator following project file:
<sysgen_tree>/examples/coregen_import/example2/coregen_imput_ex ample2.cgp
2.
As shown below, double click the FIR Compiler icon to launch the customization GUI.
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3.
Customize and generate the FIR Compiler 4.0 core with the following parameters:
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Component Name: fir_compiler_8tap
Load Coefficients: fir_compiler_8tap.coe file located in sysgen directory
Input Sampling Frequency: 25
Clock Frequency: 300
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Leave the other parameters set to the default values
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In this frame, leave the options set to the default values.
Black Box Examples
♦
Click Next >
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♦
This example will show you how to import a core that does not have a CE (clock enable) port. As shown below, verify that the CE port option is not selected, then click Generate..
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4.
CORE Generator produces the following files:
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fir_compiler_8tap.ngc
fir_compiler_8tap.vhd
fir_compiler_8tap.vho
fir_compiler_8tap.xco
: Implementation netlist
: VHDL wrapper for behavioral simulation
: Core instantiation template
: Parameters selected for core generation
Multiple .mif files: Memory initialization files for functional simulation
5.
Since this core does not have a ce port and the System Generator blackbox requires a clk
, ce pair, you need to specify a core wrapper to add a ce port to the top level.
6.
Open the following empty template wrapper file:
<sysgen_tree>/examples/coregen_import/example2/ fir_compiler_8tap_wrapper.vhd
This file contains an empty entity declaration.
7.
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Open the fir_compiler_8tap.vho file.
Copy the component declaration from fir_compiler_8tap.vho and paste it in fir_compiler_8tap_wrapper.vhd in the component declaration area.
(after -- Add Component Declaration from VHO file ------)
Copy the core instantiation template from fir_compiler_8tap.vho and paste it in fir_compiler_8tap_wrapper.vhd in the architecture body.
(after ------------- ADD INSTANTIATION Template -----)
Copy the port declaration for the component fir_compiler_8tap and paste it for the fir_compiler_8tap entity declaration
(after ---- Add Port declaration for entity ----)
Add the ce port to the top-level entity declaration, and change the case of the CLK port to clk.
8.
Start Simulink and open the following design file:
<sysgen_tree>/examples/coregen_import/example2/coregen_import_e xample2.mdl
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9.
Drag and drop the black box from the "Basic Elements" library in the coregen_import_example2.mdl
. Select fir_compiler_8tap_wrapper.vhd for the top-level HDL file.
10. Connect the black box to the open wires.
11. Open the fir_compiler_8tap_wrapper_config.m file, and add the VHDL file,
EDIF netlist and MIF files to the black box file list as shown below. These files get included as part of the System Generator netlist for the design when it is generated.
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Note:
The order in which the files are added in the configuration function is the order in which they get compiled during synthesis and simulation.
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12. Open the black box parameterization GUI and select the ISE Simulator for simulation mode.
13. Press the Simulate button to compile and co-simulate the FIR core using the ISE simulator. The simulation results are as shown below.
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