Chapter 1: Hardware Design Using System Generator requirements and would only be employed if the sample rate were very fast. An alternative approach is to clock the FIR filter at the sample rate, creating one sample per cycle. This scenario takes an intermediate amount of hardware and would be used for intermediate sample rates. If the sample rate is slow, the FIR filter may be clocked at a rate several times faster than the sample rate, perhaps by means of a DCM that multiplies the sample-rate clock. In this way the multiplier-accumulator units of the FIR filter may be reused several times during the calculation of each sample output, requiring the least amount of hardware. This last method would use a symbol-rate clock domain, a highspeed processing clock domain, and a sample-rate clock domain.
A good FPGA design practice is to have each resource in the FPGA device operating at the highest possible rate to optimize hardware usage. In general, it is best to use a single clock domain when possible and to use clock enables to gate slower circuitry, creating multicycle paths. The drawback to this technique is that it increases power consumption and may make it difficult to route the high-speed clock enable. As a result, separate domains for high-speed processing are preferable in some instances. Also, it may not be possible to avoid dealing with different clock domains when dealing with asynchronous data inputs and outputs.
Clock Domain Partitioning
Partitioning a multiple-clock design into multiple domains is an important aspect of FPGA design. System Generator uses design hierarchy to support clock domain partitioning.
More specifically, when a design uses multiple clock domains, the logic associated with each distinct clock domain should be grouped together in a Simulink subsystem.
The subsystems, or in this case, synchronous islands, are cycle-true in the sense that the hardware that is generated for an island is faithful to the Simulink behavior of the island model. The notion of bit and cycle accuracy is preserved only within the individual synchronous islands. The end model containing the synchronous islands is not necessarily cycle-true, because it drives the islands with asynchronous clocks. Although System
Generator and Simulink are able to simulate the design using ideal clock sources, the complexities involved with asynchronous clocking systems can result in discrepancies between the software simulations and hardware realizations.
The advantages to partitioning a design using subsystems are manifold:
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The physical clock lines are abstracted away from the block diagram;
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Cross-domain transfers are well-defined and can be handled with metastable-safe blocks from the Xilinx Blockset;
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Because the domains are well-defined, System Generator can accurately produce timing constraints for the synchronous islands.
The abstraction level of System Generator reduces the risk that users will perpetrate some of the more common design errors. These include:
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Gated Clocks
: because the clocks in System Generator are inferred during hardware generation, it is not possible to connect non-clock lines to clock inputs (i.e., gated clocks).
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Asynchronous Clears
: because the asynchronous resets in System Generator are inferred during hardware generation, it is not possible to explicitly clear synchronous logic using the asynchronous reset, which often results in timing problems.
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Inferred Latches
: latches will not be generated from System Generator designs.
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System Generator for DSP User Guide
UG640 (v11.4) December 2, 2009
