Chapter 1: Hardware Design Using System Generator
In the System Generator portion of a Simulink model, every signal must be sampled.
Sample times may be inherited using Simulink's propagation rules, or set explicitly in a block customization dialog box. When there are feedback loops, System Generator is sometimes unable to deduce sample periods and/or signal types, in which case the tool issues an error message. Assert blocks must be inserted into loops to address this problem.
It is not necessary to add assert blocks at every point in a loop; usually it suffices to add an assert block at one point to “break” the loop.
Note:
Simulink can display a model by shading blocks and signals that run at different rates with different colors (Format > Sample Time Colors in the Simulink pulldown menus). This is often useful in understanding multirate designs
Bit-True and Cycle-True Modeling
Simulations in System Generator are bit-true and cycle-true. To say a simulation is bit-true means that at the boundaries (i.e., interfaces between System Generator blocks and non-
System Generator blocks), a value produced in simulation is bit-for-bit identical to the corresponding value produced in hardware. To say a simulation is cycle-true means that at the boundaries, corresponding values are produced at corresponding times. The boundaries of the design are the points at which System Generator gateway blocks exist.
When a design is translated into hardware, Gateway In (respectively, Gateway Out) blocks become top-level input (resp., output) ports.
Timing and Clocking
Discrete Time Systems
Designs in System Generator are discrete time systems. In other words, the signals and the blocks that produce them have associated sample rates. A block’s sample rate determines how often the block is awoken (allowing its state to be updated). System Generator sets most sample rates automatically. A few blocks, however, set sample rates explicitly or implicitly.
Note:
For an in-depth explanation of Simulink discrete time systems and sample times, consult the
Using Simulink reference manual from the MathWorks, Inc.
A simple System Generator model illustrates the behavior of discrete time systems.
Consider the model shown below. It contains a gateway that is driven by a Simulink source
(Sine Wave), and a second gateway that drives a Simulink sink (Scope).
The Gateway In block is configured with a sample period of one second. The Gateway Out block converts the Xilinx fixed-point signal back to a double (so it can analyzed in the
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Simulink scope), but does not alter sample rates. The scope output below shows the unaltered and sampled versions of the sine wave.
Multirate Models
System Generator supports multirate designs, i.e., designs having signals running at several sample rates. System Generator automatically compiles multirate models into hardware. This allows multirate designs to be implemented in a way that is both natural and straightforward in Simulink.
Rate-Changing Blocks
System Generator includes blocks that change sample rates. The most basic rate changers are the Up Sample and Down Sample blocks. As shown in the figure below, these blocks explicitly change the rate of a signal by a fixed multiple that is specified in the block’s dialog box.
Other blocks (e.g., the Parallel To Serial and Serial To Parallel converters) change rates implicitly in a way determined by block parameterization.
Consider the simple multirate example below. This model has two sample periods, SP1 and SP2. The Gateway In dialog box defines the sample period SP1. The Down Sample block causes a rate change in the model, creating a new rate SP2 which is half as fast as SP1.
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Chapter 1: Hardware Design Using System Generator
Hardware Oversampling
Some System Generator blocks are oversampled, i.e., their internal processing is done at a rate that is faster than their data rates. In hardware, this means that the block requires more than one clock cycle to process a data sample. In Simulink such blocks do not have an observable effect on sample rates.
One block that can be oversampled is the DAFIR FIR filter. An oversampled DAFIR processes samples serially, thus running at a higher rate, but using less hardware.
Although blocks that are oversampled do not cause an explicit sample rate change in
Simulink, System Generator considers the internal block rate along with all other sample rates when generating clocking logic for the hardware implementation. This means that you must consider the internal processing rates of oversampled blocks when you specify the Simulink system period value in the System Generator block dialog box.
Asynchronous Clocking
System Generator focuses on the design of hardware that is synchronous to a single clock.
It can, under some circumstances, be used to design systems that contain more than one clock. This is possible provided the design can be partitioned into individual clock domains with the exchange of information between domains being regulated by dual port memories and FIFOs. System Generator fully supports such multi-clock designs, including the ability to simulate them in Simulink and to generate complete hardware descriptions.
Details are discussed in the topic
Generating Multiple Cycle-True Islands for Distinct
Clocks . The remainder of this topic focuses exclusively on the clock-synchronous aspects
of System Generator. This discussion is relevant to both single-clock and multiple-clock designs.
Synchronous Clocking
As shown in the figure below, when you use the System Generator token to compile a design into hardware, there are three clocking options for Multirate implementation: (1)
Clock Enables (the default), (2) Hybrid DCM-CE, and (3) Expose Clock Ports.
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The Clock Enables Option
When System Generator compiles a model into hardware with the Clock Enable option selected, System Generator preserves the sample rate information of the design in such a way that corresponding portions in hardware run at appropriate rates. In hardware,
System Generator generates related rates by using a single clock in conjunction with clock enables, one enable per rate. The period of each clock enable is an integer multiple of the period of the system clock.
Inside Simulink, neither clocks nor clock enables are required as explicit signals in a
System Generator design. When System Generator compiles a design into hardware, it uses the sample rates in the design to deduce what clock enables are needed. To do this, it employs two user-specified values from the System Generator block: the Simulink system period and FPGA clock period. These numbers define the scaling factor between time in a
Simulink simulation, and time in the actual hardware implementation. The Simulink system period must be the greatest common divisor (gcd) of the sample periods that appear in the model, and the FPGA clock period is the period, in nanoseconds, of the system clock. If p represents the Simulink system period, and c represents the FPGA system clock period, then something that takes kp units of time in Simulink takes k ticks of the system clock (hence kc nanoseconds) in hardware.
To illustrate this point, consider a model that has three Simulink sample periods 2, 3, and
4. The gcd of these sample periods is 1, and should be specified as such in the Simulink
System Period field for the model. Assume the FPGA Clock Period is specified to be 10ns.
With this information, the corresponding clock enable periods can be determined in hardware.
In hardware, we refer to the clock enables corresponding to the Simulink sample periods 2,
3, and 4 as CE2, CE3, and CE4, respectively. The relationship of each clock enable period to the system clock period can be determined by dividing the corresponding Simulink sample period by the Simulink System Period value. Thus, the periods for CE2, CE3, and
CE4 equal 2, 3, and 4 system clock periods, respectively. A timing diagram for the example clock enable signals is shown below:
The Hybrid DCM-CE Option
If the implementation target is an FPGA with a Digital Clock Manager (DCM), you can choose to drive the clock tree with a DCM. The DCM option is desirable when high fanout on clock enable nets make it difficult to achieve timing closure.
System Generator instantiates the DCM in a top-level HDL clock wrapper and configures the DCM to provide up to three clock ports at different rates for Virtex®-4 and Virtex®-5 and up to two clock ports for Spartan-3A DSP . If the design has more clock ports than the DCM can support, the remaining clocks are supported with the CE (clock enable) configuration.
The mapping of rates to the DCM outputs is done according to the following priority scheme:
CLK0 > CLK2x > CLKdv > CLKfx. The DCM supports the higher clock rates first.
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Chapter 1: Hardware Design Using System Generator
A dcm_reset input port is exposed on the top-level wrapper to allow the external design to reset the DCM after bitstream configuration. A dcm_locked output port is also exposed to help the external design synchronize the input data with the single clk input port.
Known Limitations
: The following System Generator blocks are not supported by the
Hybrid DCM-CE Option:
•
Clock Enable Probe
•
Clock Probe
•
DAFIR
•
Downsample - when the Sample option First value of the frame is selected
•
FIR Compiler - when the core rate is not equal to the input sample rate
•
Parallel to Serial- when the Latency option is specified as 0 (zero)
•
Time Division De-Multiplexer
•
Time Division Multiplexer
•
Upsample - when the Copy samples (otherwise zeros are inserted) option is not selected.
The Expose Clock Ports Option
When you select this option, System Generator creates a top-level wrapper that exposes a clock port for each rate. You can then manually instantiate a clock generator outside the design to drive the clock ports.
Tutorial Example: Using the Hybrid DCM-CE Option
The following step-by-step example will show you how to select the Hybrid DCM-CE option, netlist the HDL design, implement the design in ISE®, simulate the design and examine the files and reports to verify that the DCM is properly instantiated and configured.
The hybrid_dcm_ce_case1.mdl design example is located at the following pathname
<sysgen_tree>/examples/clocking_options/hybrid_dcm_ce_case1/hybrid
_dcm_ce_case1.mdl
1.
Open the model in MATLAB and observe the following blocks:
•
Addressable Shift Register (ASR)
: used to implement the input delay buffer. The address port runs n times faster than the data port, where n is the number of the filter taps (5 for this example)
•
Coefficient ROM
: used to store the filter coefficients
•
Counter
: used to generate addresses for the ROM and ASR
•
Comparator
: used to generate the reset and enable signals
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•
MAC Engine
: used as a Multiply-Accumulator operator for the filter
2.
Double-click on the System Generator token to bring up the following dialog box:
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Chapter 1: Hardware Design Using System Generator
As shown, select Hybrid DCM-CE, then click Generate. After a few moments, a subdirectory named hdl_netlist_dcm is created in the current working directory containing the generated files.
3.
In the MATLAB Current Directory window, double-click on the file hybrid_dcm_ce_case1_sysgen.log. As shown below, the DCM clocks are listed first (highest rates first), followed by the CE driven clocks.
4.
Launch ISE, then load the ISE project at pathname
./hdl_netlist_dcm/hybrid_dcm_ce_case1_dcm_mcw.ise
5.
Under the Project Navigator Processes tab, double-click on Implement Design.
6.
From the Project Navigator Sources tab, do the following: a.
Double-click on the file hybrid_dcm_ce_case1_dcm_mcw.vhd, then scroll down to view the DCM component declaration as shown below by the VHDL code snippet: b. Observe that System Generator automatically infers and instantiates the DCM instance and its parameters according to the required clock outputs.
c.
Close the VHDL file.
Next, you are going to examine the clock propagation by examining the ISE timing report.
First, you must generate the report.
7.
Open the following folder: Processes tab > Implement Design > Place & Route >
Generate Post-Place & Route Static Timing
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8.
Double -click on Analyze Post-Place & Route Static Timing and you should see the information in the figure below:
This design is comprised of six clock rates – 1, 2, 4, 8, 20, 40 with respect to the 10 ns global clock constraint. The timing report validates the correct clock generation and propagation by System Generator as follows:
♦
♦
DCM-based clocks
: clk_1 (CLK0 ->10 ns), clk_2 (CLKFX ->20 ns) , clk_4 (CLKDIV
->40 ns) generated by the DCM based on the 10 ns global clock input
Clock Enable-based clocks
: ce_8 (80 ns), ce_20 (200 ns), ce_40 (400 ns) generated by clock enables based on the clk_4 clock input
Next you want to perform a behavior simulation using the ModelSim.
9.
As shown in the following figure, move to the Sources for dialog box in the Sources window, then select Behavioral Simulation
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Chapter 1: Hardware Design Using System Generator
Note:
System Generator automatically creates the top-wrapper VHDL testbench, script file and input/output stimulus data files. The Processes tab changes and displays according to the
Sources type being selected.
1. Select
2. Double Click
10. Simulate the design, as shown above, by double-click on Simulate Behavioral Model in the Processes window
11. After the simulation is finished, you should be able to observe the simulation waveforms as shown in the figure below:
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All DCM clocks are included in the top-level wrapper testbench file
(hybrid_dcm_ce_case1_dcm_mcw_tb.vhd) – clk_1, clk_2 and clk_4.
Summary
When you select the Hybrid DCM-CE option, System Generator automatically infers and instantiates a DCM without further manual intervention. In addition, the tool intelligently generates different clock rates by using a combination of DCM and CE clock generation algorithms and by assigning appropriate clock rates to either the DCM or CE in order to obtain optimal Quality of Results and low power consumption. You do not have to set attributes or specify DCM clock outputs. You should expect minimal clock skew when selecting the Hybrid DCM-CE option compared to the Clock Enables option alone.
Tutorial Example: Using the Expose Clock Ports Option
The following step-by-step example will show you how to select the Expose Clock Ports option, netlist the HDL design, implement the design in ISE, simulate the design, then examine the files and reports to verify the design.
The expose_clock_ports_case1 design example is located at the following pathname
<sysgen_tree>/examples/clocking_options/expose_clock_ports_case1/e xpose_clock_ports_case1.mdl
1.
Open the model in MATLAB and observe the following blocks:
•
Addressable Shift Register (ASR)
: used to implement the input delay buffer. The address port runs n times faster than the data port, where n is the number of the filter taps (5 for this example)
•
Coefficient ROM
: used to store the filter coefficients
•
Counter
: used to generate addresses for the ROM and ASR
•
Comparator
: used to generate the reset and enable signals
•
MAC Engine
: used as a Multiply-Accumulator operator for the filter
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Chapter 1: Hardware Design Using System Generator
2.
Double-click on the System Generator token to bring up the following dialog box:
As shown above, select Expose Clock Ports, then click Generate. After a few moments, a sub-directory named hdl_netlist is created in the current working directory containing the generated files.
3.
Launch ISE, then load the ISE project at pathname
./hdl_netlist/expose_clock_ports_case1_mcw.ise
4.
Under the Project Navigator Processes tab, double-click on Implement Design.
5.
From the Project Navigator Sources tab, do the following: a.
double-click on the file expost_clock_ports_case1_mcw.vhd, then scroll down to view the entity named expose_clock_ports_mcw, as shown below:
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b. Observe that System Generator infers the clocks based on the different rates in the design and brings the clock ports to the top-level wrapper. Since this design contains two clock rates, clocks clk_1 and clk_5 are pulled to the top-level wrapper. This will allow you to directly drive the multiple synchronous clocks from outside the System Generator design.
c.
Close the VHDL file.
Next you want to perform a behavior simulation using the ModelSim. www.xilinx.com
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6.
As shown below, move to the Sources for dialog box in the Sources window, then select Behavioral Simulation
Note:
System Generator automatically creates the top-wrapper VHDL testbench, script file and input/output stimulus data files. The Processes tab changes and displays according to the
Sources type being selected.
1. Select
2. Double Click
7.
Simulate the design, as shown above, by double-click on Simulate Behavioral Model in the Processes window
8.
After the simulation is finished, you should be able to observe the simulation waveforms as shown in the figure below:
Summary
When you select the Expose Clock Ports option, System Generator automatically infers the correct clocks from the design rates and exposes the clock ports in the top-level wrapper.
The clock rates are determined by the same methodology when you use the Clock Enables option. You can now drive the exposed clock ports from an external synchronous clock source.
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