Chapter 4: Importing HDL Modules
Importing a VHDL Module
Black Box Tutorial Example 3: Importing a VHDL Module
This topic explains how to use the black box to import VHDL into a System Generator design and how to use ModelSim to co-simulate the VHDL module.
1.
From the MATLAB console, change the directory to
<sysgen_tree>/examples/black_box/intro
.
The following files are located in this directory:
♦ black_box_intro.mdl
- A Simulink model containing an example black box.
♦ transpose_fir.vhd
- Top-level VHDL for a transpose form FIR filter. This file is the VHDL that is associated with the black box.
♦ mac.vhd
– Multiply and add component used to build the transpose FIR filter.
2.
Open the black_box_intro model from the MATLAB command window by typing
>> black_box_intro
3.
Open the subsystem named Transpose FIR Filter Black Box. At this point, the subsystem contains two inports and one outport. The black box subsystem is shown below:
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4.
Go to the Simulink Library Browser and add a black box block to this subsystem. The black box is located in the Xilinx Blockset's Basic Elements library. The Black Box
Configuration Wizard is automatically invoked when a new black box is added to the subsystem. A browser window appears that lists the VHDL source files that can be www.xilinx.com
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Black Box Examples
associated with the black box. From this window, select the top -level VHDL file transpose_fir.vhd
. This is illustrated in the figure below:
Note:
The wizard will only run if the black box is added to a model that has been saved to a file. If the model has not been saved, the wizard does not know where to search for files and System
Generator will instead display a warning that looks like the following:
5.
The wizard parses the VHDL to generate a configuration M-function for the black box.
This is a MATLAB script that, among other things, associates the black box to the
VHDL and creates black box ports. Once the function has run, the ports on the black box match those in the top-level VHDL entity (not including clock and clock enable ports). This is illustrated below:
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Chapter 4: Importing HDL Modules
Be aware of the following rules when working this example:
♦
A synchronous HDL design that is associated with a black box must have one or more clock and clock enable ports. These ports must occur in pairs, one clock for each clock enable, and vice-versa. Each of these ports must be of type std_logic.
The name of the clock port must contain the substring clk. The name of the clock enable port must be the same as the name of the clock port, but with ce substituted for clk.
♦
The clock enable port has a specific meaning to System Generator and is not a general purpose user enable for the block. Refer to the topic
Black Box HDL
Requirements and Restrictions
for details.
6.
Double click on the black box block. The dialog box shown below appears:
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The following are the fields in the dialog box:
♦
♦
Block configuration M-function
- This specifies the name of the configuration Mfunction for the black box. In this example, the field contains the name of the function that was generated by the Configuration Wizard. By default, the black box uses the function the wizard produces. You can, however, substitute one you produce yourself. For more information on the configuration M-function, refer to
the topic Black Box Configuration M-Function .
Simulation mode
- There are three simulation modes:
Inactive
- When the mode is Inactive, the black box participates in the simulation by ignoring its inputs and producing zeros. This setting is typically used when a separate simulation model is available for the black box, and the model is wired in parallel with the black box using a simulation multiplexer.
Black Box Tutorial Example 1: Importing a Core Generator
Module that Satisfies Black Box HDL Requirements
shows how this is accomplished.
ISE Simulator
- When the mode is ISE Simulator, simulation results for the black box are produced using co-simulation on the HDL associated to the black box. www.xilinx.com
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♦
External co-simulator
- When the mode is External co-simulator, it is necessary to add a ModelSim HDL co-simulation block to the design, and to specify the name of the ModelSim block in the field labeled HDL co-
simulator to use
. In this mode, the black box is simulated using HDL cosimulation.
FPGA Area Estimation
- The numbers entered in this field are estimates of how much of the FPGA is used by the HDL for the black box. These numbers must be entered by hand. The numbers are only needed if you would like to use the resource estimating utilities supplied with System Generator. For more
information, see Resource Estimation .
To continue the tutorial, leave the parameters set as they currently are.
7.
Wire the black box's ports to the corresponding subsystem ports.
8.
Run the simulation by clicking the Simulation Play button and then double click on the scope block. Notice the black box output shown in the Output Signal scope is zero.
This is expected as the black box is configured to be inactive during simulation.
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Chapter 4: Importing HDL Modules
9.
Go to the Simulink Library Browser and add a ModelSim block to this subsystem. The
ModelSim block is located in the Xilinx Blockset /Tools library. This block enables the black box to communicate with a ModelSim simulator. Double click on the ModelSim block to open the dialog box shown below:
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10. Make sure the parameters match those shown in the preceding figure. Close the dialog box.
11. From the Simulink menu, select Port Data Types from the Format menu to display the port types for the black box. Compile the model (Ctrl-d) to ensure the port data types are up to date. Notice that the black box port output type is UFix_26_0. This means it is unsigned, 26 bits wide and has a binary point 0 positions to the left of the least significant bit.
12. Open the configuration M-function transpose_fir_config.m and change the output type from UFix_26_0 to Fix_26_12. The modified line should read: dout_port.setType('Fix_26_12');
13. Edit the configuration M-function to associate an additional HDL file with the black box. Locate the line: this_block.addFile('transpose_fir.vhd');
Immediately above this line, add the following: this_block.addFile('mac.vhd'); www.xilinx.com
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14. Save the changes to the configuration M-function and recompile the model (Ctrl-d).
Your subsystem should appear as follows:
15. From the black box block parameter dialog box, change the Simulation mode field from Inactive to External co-simulator. Enter ModelSim in the HDL co-simulator to
use
field. The name in this field corresponds to the name of the ModelSim block that you added to the model. The black box dialog box should appear as follows:
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16. Run the simulation. A ModelSim command window and waveform viewer opens.
ModelSim simulates the VHDL while Simulink controls the overall simulation. The resulting waveform looks something like the following:
The following warnings received in ModelSim can safely be ignored.
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
# Time: 0 ps Iteration: 0 Instance: / xlcosim_black_box_ex1_down_converter_transpose_fir_filter_bl ack_box_modelsim/ black_box_ex1_down_converter_transpose_fir_filter_black_box_ black_box/g0__22/g_last/m2
They are caused by the black box VHDL not specifying initial values at the start of simulation.
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