3.3 Analog blocks. Infineon CY8C4045LQI-S412, CY8C4045LQI-S413, CY8C4025AZI-S413T, CY8C4024LQI-S412, CY8C4025AZQ-S403, CY8C4024LQI-S403T, CY8C4025LQI-S412, CY8C4025LQI-S402T, CY8C4045LQI-S411, CY8C4024AXI-S412

PSoC™ 4 MCU: PSoC™ 4000S

Based on Arm® Cortex®-M0+ CPU

Functional definition

3.2.6

Watchdog timer

A watchdog timer is implemented in the clock block running from the ILO; this allows watchdog operation during

Deep Sleep and generates a watchdog reset if not serviced before the set timeout occurs. The watchdog reset is recorded in a Reset Cause Register, which is firmware readable.

3.2.7

Reset

The PSoC™ 4000S can be reset from a variety of sources including a software reset. Reset events are asynchronous and guarantee reversion to a known state. The reset cause is recorded in a register, which is sticky through reset and allows software to determine the cause of the reset. An XRES pin is reserved for external reset by asserting it active low. The XRES pin has an internal pull-up resistor that is always enabled.

3.2.8

Voltage reference

The PSoC™ 4000S reference system generates all internally required references. A 1.2-V voltage reference is provided for the comparator. The IDACs are based on a ±5% reference.

3.3

Analog blocks

3.3.1

Low-power comparators (LPC)

The PSoC™ 4000S has a pair of low-power comparators, which can also operate in Deep Sleep modes. This allows the analog system blocks to be disabled while retaining the ability to monitor external voltage levels during low-power modes. The comparator outputs are normally synchronized to avoid metastability unless operating in an asynchronous power mode where the system wake-up circuit is activated by a comparator switch event.

The LPC outputs can be routed to pins.

3.3.2

Current DACs

The PSoC™ 4000S has two IDACs, which can drive any of the pins on the chip. These IDACs have programmable current ranges.

3.3.3

Analog multiplexed buses

The PSoC™ 4000S has two concentric independent buses that go around the periphery of the chip. These buses

(called amux buses) are connected to firmware-programmable analog switches that allow the chip’s internal resources (IDACs, comparator) to connect to any pin on the I/O Ports.

3.4

Programmable digital blocks

The programmable I/O (Smart I/O) block is a fabric of switches and LUTs that allows boolean functions to be performed in signals being routed to the pins of a GPIO port. The Smart I/O can perform logical operations on input pins to the chip and on signals going out as outputs.

Datasheet 12 002-00123 Rev. *O

2022-07-28